Implementation in fpga and choice of pins

[slearn]

I am using Nexys 4 DDR Artix 7 Fpga board. I would like to know if I could implement the following block.

What will be the choice of pins through which I could give the analog inputs and which pin will be ideal for observing the output from.

Will there be  any code that I should run to implement this

I am using analog discovery 1 for giving the analog inputs

[zygot]

@slearn,

I noticed that this post is similar to another one in which the target is possibly a Virtex5 FPGA.

Asking hardware interface questions on a forum like this and providing partial or incomplete information as to exactly what you intend to do is a good way to get bad advice and into trouble.

In the interests of smoke-free FPGA development could you be a bit more specific as to what you want to accomplish. I think that I have an idea as to what your idea is... but knowing is better than thinking. In the diagram I notice that one of your inputs is unconnected.

Without any other information to work with my only suggestion would be to read the FPGA data sheet and supporting materials to understand what the input pin dc specifications are. Driving any FPGA pin beyond those limits will damage your device.

[xc6lx45]

Hi,

you need two ends of a differential input.

Check the schematic, page 7:
https://reference.digilentinc.com/_media/reference/programmable-logic/nexys-4-ddr/nexys-4-ddr_sch.pdf

For example, JA1 and JA3 form such a pair. They go to package pads C17 and E18, and on the FPGA they are IO_L20P_... and IO_L20N_...
The L20P and -N is crucial here.

Your next stop should be https://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf e.g. page 36 (BUFDS/IBUFGDS).
Most likely, you can disregard anything related to "HP" banks on this small FPGA, only "HR" is available.

From an electrical point-of-view, note page 36:

...and from the device pads to show the P and N channel pins in a differential pair.

which is your 1-bit ADC / analog comparator.