FPGA - ARTY DDR3

[dromeo116]

Has anyone interfaced to the DDR3 memory on the arty development board not using a microblaze interface ? Looking for examples on how to interface the DDR3 to a simple state machine where i need to read in a lot of values from a ADC. 

[TommyK]

Hi dromeo116,

I haven't tried myself, but I have interfaced with DDR using a Nexys4 DDR as well as the Nexys Video. We use a DDR module along with the MIG in our Looper Projects. Check it out on our Wiki. You might also like to try to adapt the SRAM to DDR component to use with the Arty's DDR3. That's what I did for the Looper. One thing you'll need to remember is to clock sys_clk_i with a 166.667MHz clk and clk_ref_i with a 200MHz clk. Let me know if you have any questions.

Tommy

[wfjmueller]

Hi,

I just tried to generate a MIG core for Arty. Under Vivado 2015.4. Used as a starting point the prj and ucf provided by Digilent as arty_mig_ddr3.zip.

When I imported the mig.prj the core generator complained with an ERROR about a part mismatch. A quick look into mig.prj shows

    <TargetFPGA>xc7a15ti-csg324/-1L</TargetFPGA>

The Arty uses a 35 die size Artrix-7, not a 15 die size. Simply wrong part. If elementary things like this are wrong, how should I trust the rest ?

[TommyK]

Hi wfjmueller,

Sorry about that! Those files were meant for the Arty version B.0 which used a 15 die size Artix-7. We have moved to Github since that zip was uploaded, so you can find the new files in the Arty/Resources/Arty_MIG_DDR3 folder. Here is a link to the Arty repo.

Hope this helps!

Tommy