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issue with xadc auxiliary input simulation


farhanazneen

Question

hello 

xadc simulation issue never ends i was trying since past  3 weeks to simulate xadc with auxiliary input  vaux0 (zedboard xadc header pin) sinewave   but always stuck with the errors.Always there  is  warnings showing up  top module is not defined and undeclared parameters.Below is the attachments of main module , test bench and instantiation of ip. Please do let me know where iam making mistakes or else please provide me a main module & testbench  code with auxiliary input .

please provide me a mainmodule and testbench code with auxiliary input zedboard.

 

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Hi @farhanazneen,

Looking a little closer it appears you are trying to simulate just the xadc ip core.  I did find a xilinx tutorial that does this for a different IP and Dev board but should be a helpful reference.  You might find it easier to simulate a project then just the IP Core. Here is an hdl xadc project for the Zybo that should be relatively easy to get working on the Zedboard.

thank you,

Jon

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