Extremely exact clock frequency

[dgottesm]

Hi

I am inputting an external clock into my Basys3. I want to input the clock into a clock wizard and the output of the clock wizard would be a clock of the same frequency, and a clock of half the frequency, so hypothetically,  not a tall order. The problem is that the data sheet of the clock (and the data coming with it) says the frequency of the clock is 28.63636 MHz, +- 50 ppm. So, I typed into the clock wizard the exact frequency for the input and the two outputs, and when I tried to implement, it failed and I got the following message:

[DRC 23-20] Rule violation (PDRC-43) PLL_adv_ClkFrequency_div_no_dclk - The computed value 755.980 MHz (CLKIN1_PERIOD, net clk_54_in_clk_wiz_2) for the VCO operating frequency of the PLLE2_ADV site PLLE2_ADV_X0Y2 (cell clk_wiz_2/inst/plle2_adv_inst) falls outside the operating range of the PLL VCO frequency for this device (800.000 - 1600.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input period CLKINx_PERIOD (18.518997), multiplication factor CLKFBOUT_MULT_F (14) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

So what should I do? I know that it is a PLL, so hypothetically, I can give it an easier frequency that is close enough to the actual frequency and let the PLL lock on to the actual frequency. Any comments or suggestions? 

[D@n]

@dgottesm,

A couple things to note.  First, the PLL implementation in 7-series devices is a subset of what the MMCMs can do.  You may wish to try switching to an MMCM instead of a PLL.

Looking over the clocking specification, what you are asking for appears to be well within the limits of what is possible.  May I suggest that if you want a PLL implementation, that you instantiate it yourself apart from the wizard?  That'll allow you to set the CLKFBOUT_MULT_F (multiplication) value so that the intermediate frequency is between 800MHz and 1600MHz, and then the CLKOUT_DIVIDE value to be something near where you want.  I've personally only ever directly instantiated the PLL's, and they aren't hard to do at all.  (Not like the iCE40 PLLs--those are next to impossible to get right.)

Dan

[D@n]

@dgottesm,

Why not just run the clock directly into a global buffer, and then use a OBUF to output the half rate clock?  You can use the full rate clock within your design, and create the second clock logically on an output.  As an off-hand guess, I doubt the frequencies involved are so high and the phase tolerances so tight that you actually need the PLL.

Dan

[dgottesm]

@D@n

thanks for your answer. Can you please tell me in a straightforward way how to route an input to a BUFG? I have heard of it, but I can’t find someone saying how. 

What does an OBUF do and how does it half the clock rate?

I have heard that it is unwise to half a clock logically ie with a flip flop.

i don’t specifically want a PLL, an MMCM is fine if it gets the job done. 

I have never instantiated a PLL (or any primitive for that matter). I have only used the Vivado wizards.

[D@n]

I just instantiate a BUFG anytime I need it.  In verilog, it looks like,

wire bufg_input, bufg_output;

assign bufg_input = clock_input_pin;

BUFG mybufg(.I(bufg_input), .O(bufg_output));

After this, you'll want to avoid using bufg_input or clock_input_pin anymore.  Make all your references to bufg_output instead.

A bufg by itself doesn't halve the clock rate, it just places the incoming clock wire onto one of the high speed global clock distribution nets within your design.

But let's come back to the dividing a clock by two.  Is it unwise?  Yes.  If the divided clock is only going directly to an output port, it might work.  You may have a problem that one design will have one phase relationship between the two clocks and another design will have another. 

An alternative, again if you are only driving an output port, might be to use an ODDR module.  For outputting the original clock, send a 2'b10 to the ODDR module.  For outputting the halved clock, send alternating 2'b00 and 2'b11 to it.  Since the ODDR module has a fixed relationship to the pin, it guarantees a phase relationship on the output port.

Now, regarding that half clock rate clock, do you need it within your FPGA?  Or can you use the full rate clock and only operate on every other cycle as determined by a logical chip enable?

Dan

[dgottesm]

@D@n

thanks for the tip on instantiating a BUFG

yes, I need the halved clock for the design/logic as well. But I suppose I can half the clock locally in the module using an enable bit... it just means that I have to add that in my design. I already designed to receive a half clock...

[D@n]

In general, you should want to do everything in the same clock domain.  Crossing clock domains is usually considered a potential source of errors that can be hard to debug.

Dan

[xc6lx45]

Hi,

can you try to enter the numbers again on a clean (e.g. dummy design)?

I tried with Clk Wizard V6.0 and it accepts them:

clk_in1:28.63636
clk_out1: 28.63636
clk_out2: 57.2727200000000

It requires no other changes from the default values (possibly the input buffer, as in your other question). The resulting VCO frequency is 973.636 MHz, the multiplier 34 and the dividers 34 (surprise...) and 17.