8 bit even parity check

[TJ]

Hello,

Does the below look like acceptable vhdl  code for the 8 bit even parity check?

 

CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pairity is
generic(n:integer:=7);
port(a:in std_logic_vector(n-1 downto 0);
b:out std_logic_vector(n downto 0));
end pairity;

architecture Behavioral of pairity is

begin
process(a)
            variable temp1:std_logic;
            variable temp2:std_logic_vector(b'range);
            begin
                        temp1:='0';
                        for i in a'range loop
                                    temp1:=temp1 xor a(i);
                                    temp2(i):=a(i);
                        end loop;
                                    temp2(b'high):=temp1;
                                    b<=temp2;
end process;

end Behavioral;

 

 

Thanks,

TJ

[hamster]

It looks fine - however a few questions

1) Did you mean to spell "parity" as "pairity"?

2) Why do you have the three 'use' statements - only one is really needed?

3) Only the upper bit of 'b' needs to be assigned in the process. If you assign "b(n-1 downto 0) <= a;" you can remove the 'temp2' variable.

Mike

[TJ]

Thank you very much.  Yes I did mean parity.  Spelling error.  The 3 use statements is old habits.  Good point about temp2 variable.

Thanks,

TJ