kishoreS Posted August 2, 2018 Share Posted August 2, 2018 Guys how do I create a design.txt file for the Xilinx FPGA ? I want to test the system monitor logic core for the FPGA . How do I simulate the analog input? Link to comment Share on other sites More sharing options...
jpeyron Posted August 2, 2018 Share Posted August 2, 2018 Hi @kishoreS, The XADC Wizard v3.3 LogiCORE IP Product Guide on page 41 discusses that the default name and path for the analog stimulus is design.txt generated in the core simulation area. The Vivado Design Suite User Guide: Logic Simulation should help with simulation and analog signal. thank you, Jon Link to comment Share on other sites More sharing options...
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kishoreS
Guys how do I create a design.txt file for the Xilinx FPGA ? I want to test the system monitor logic core for the FPGA . How do I simulate the analog input?
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