Pattern Generator DO connected to Logic Analyzer DI

[Venkat]

Hi,

I am new user of DD.

I am developing python script to send custom data on pattern generator and receive it on logic analyzer and then do data integrity check (as of now dumping the data to csv file and later need to modify to compare the data). 

when run the Python script (see below) , I see all '0' in csv file.

Appreciate if anybody provide me insight on how to achieve this task.

 

Below  is pattern generator related code: 

channel = 0
dwf.FDwfDigitalOutEnableSet(hdwf, channel, c_int(1))
dwf.FDwfDigitalOutTypeSet(hdwf, channel, DwfDigitalOutTypeCustom)
cBits = 16
rgdData = (2*c_byte)(*[0x12,0x34])
dwf.FDwfDigitalOutDataSet(hdwf, channel, byref(rgdData), c_int(cBits))
dwf.FDwfDigitalOutRunSet(hdwf, c_double(2*8/1e8)) # 160ns = 2*8 bits /100MHz = 16 bits * 10ns
dwf.FDwfDigitalOutRepeatSet(hdwf, c_int(1)) # once
print('PG Setup Done: Channel ',channel)

And below is Logic Analyzer related code:

dwf.FDwfDigitalInTriggerSourceSet(hdwf, trigsrcDigitalIn)
dwf.FDwfDigitalInTriggerSet(hdwf, 0,0,0xFFFF,0xFFFF);
dwf.FDwfDigitalInTriggerAutoTimeoutSet(hdwf, c_double(10.0));
#sample rate = system frequency / divider, 800MHz/8 = 100MHz sample rate
dwf.FDwfDigitalInDividerSet(hdwf, c_int(8))
# 16bit per sample format
dwf.FDwfDigitalInSampleFormatSet(hdwf, c_int(16))
# set number of sample to acquire
cSamples = 16
#rgwSamples = (c_uint16*cSamples)()
rgwSamples = (c_uint8*cSamples)()
dwf.FDwfDigitalInBufferSizeSet(hdwf, c_int(cSamples))
 

Both LA and PG are configured:

# begin acquisition # Enable LA
dwf.FDwfDigitalInConfigure(hdwf, c_bool(0), c_bool(1))
# Enable PG
dwf.FDwfDigitalOutConfigure(hdwf, c_int(1))

Below is Acquisition code:

while True:
    dwf.FDwfDigitalInStatus(hdwf, c_int(1), byref(sts))
    print ('STS VAL: ', str(sts.value))
    if sts.value == stsDone.value :
        break
    time.sleep(1)
print ('Acquisition finished')

 

And below is read data code:

# get samples, byte size
#dwf.FDwfDigitalInStatusData(hdwf, rgwSamples, 2*cSamples)
dwf.FDwfDigitalInStatusData(hdwf, rgwSamples, 1*cSamples)
dwf.FDwfDeviceCloseAll()

For the time being writing to csv file:

f = open("record.csv", "w")
for v in rgwSamples:
    f.write("%s\n" % v)
f.close()
 

Regards,
Venkat

 

 

digilent_examp.py

[attila]

Hi @Venkat

See the following script AnalogOut_Custom.py DigitalOut_Custom.py

The issues regarding your code:
- instead trigsrcDigitalIn use trigsrcDetectorDigitalIn for LA  or directly trigger on trigsrcDigitalOut
- for FDwfDigitalInSampleFormatSet 16 (bit samples DIN0..15) use FDwfDigitalInStatusData with 2* (16 bit = 2 byte samples)
- use FDwfDigitalInTriggerPositionSet to configure how many samples to capture after trigger, with default 0 the T0 will be on the right of the buffer

[Venkat]

Hi Aiila,

First of all very big thank you for responding so quickly and promptly.

As you mentioned I have modified/used:

dwf.FDwfDigitalInTriggerSourceSet(hdwf, trigsrcDetectorDigitalIn)

dwf.FDwfDigitalInSampleFormatSet(hdwf, (2))

dwf.FDwfDigitalInTriggerPositionSet (handle, c_int(4*8-1))  #4 bytes are sent on PG and need to be captured on LA

 

And increased data to be sent to 4Bytes

cSamples = 32

When DigitalInTriggerPositionSet to 32, LA read buffer doesn't have the 1st bit sent on PG. Hence I have set the value to 31, LA read buffer contains the 1st bit sent on PG.

With the above settings and all other settings mentioned in the origital thread, I see last 4 bits either not captured on LA or not stored in to DigitalInBuffer as in below:

PG Channel- 1 data: 01110100  11001011  01001001  11100011

LA Status Check
Acquisition finished

LA Channel-1 data: 00101110 11010011 10010010 11000000

Could you please clarify

1) why 1st bit is missing in the capture when FDwfDigitalInTriggerPositionSet to 32 (exact cnt)

2). why the last 4 bits are missing in the capture.

 

Regards,

Venkt

 

 

 

[Venkat]

Hi Attila,

Just wanted to update on the LA behavior:

Problem was not last 4 bits. It can be 3 bits or 5 bits.. as shown  below

PG Channel- 1 data: 01110011  11000111  11101110  00011110

LA Status Check
Acquisition finished

LA Channel-1 data: 11001110 11100011 01110111 01100000

 

Regards,

Venkat

[attila]

Hi @Venkat

I'm not sure why is this +/-1 trigger position problem with the detector...
Please try to use the triggering on digital-out which gives correct trigger position.
dwf.FDwfDigitalInTriggerSourceSet(hdwf, trigsrcDigitalOut)

[Venkat]

Hi Attilia,

Thanks your suggestion for using the dwf.FDwfDigitalInTriggerSourceSet(hdwf, trigsrcDigitalOut).

Looks like this change solves the +/-1 trigger position.

Now the LA capture data is matching with PG data at the trigger position.

Some how it still doesn't match last few bits (mismatch varies from run to run). Please see below  different run results.

Run_1: (3 bit mismatch)

PG Channel-0 data: 01110101 11001011 01001001 11111111
LA Status Check
STS VAL:  2
Acquisition finished

LA Channel-0 data: 10101110 11010011 10010010 11111000

Run_2: (2 bit mismatch)

PG Channel-0 data: 01110101 11001011 01001001 11111111
LA Status Check
STS VAL:  2
Acquisition finished

LA Channel-0 data: 10101110 11010011 10010010 11111100
 

Run_3: (5 bit mismatch)

PG Channel-0 data: 01110101 11001011 01001001 11111111
LA Status Check
STS VAL:  2
Acquisition finished

LA Channel-0 data: 10101110 11010011 10010010 11100000

 

Attached is the copy of the script I am using at my end. If you could look into this (also you should be able to use as is), and let me know 

if there is any issue with my script, that would be great.

Regards,
Venkat

 

digilent_pg_to_la.py

[attila]

Hi @Venkat

I just notice that earlier I have attached AnalogOut_Custom instead DigitalOut_Custom...

Here you have your script with a few modifications, noted with !!!
digilent_pg_to_la.py

#! python

# -----------------------------------------
# Digilent Utility
# -----------------------------------------

from ctypes import *
from dwfconstants import *
import sys
import time
import math


dwf = cdll.dwf

hdwf = c_int()
sts = c_byte()

hzSys = c_double()
channel = c_int(0)
cBits = 4*8
rgdSamples = (c_byte*4)(*[0x75,0xCB,0x49,0xFF])
cSamples =5*8

# !!! for 8 bit samples use c_uint8
# for 16 bit samples use c_uint16 and specify 2x size in FDwfDigitalInStatusData since it is 2byte/sample
# for 32 bit samples use c_uint32 and specify 4x size in FDwfDigitalInStatusData since it is 4byte/sample
rgSamples = (c_uint8*cSamples)() 

#Open device
dwf.FDwfDeviceOpen(c_int(-1), byref(hdwf))

# print ('PG Channel-0 data: 01110101 11001011 01001001 11111111') wrong

# !!! the output is least significant bit first like 10101110 instead 01110101
print('PG Channel-0 data: ', end="")
for v in rgdSamples:
    for i in range(8):
        print((v&1),end="")
        v >>= 1
    print(' ', end="")
print('\n')

dwf.FDwfDigitalOutReset(hdwf)
dwf.FDwfDigitalInReset(hdwf)
#PG Setup

dwf.FDwfDigitalOutInternalClockInfo(hdwf, byref(hzSys))

#dwf.FDwfDigitalOutWaitSet (hdwf, c_double(1e-3)) #BV: Added extra recently

dwf.FDwfDigitalOutEnableSet(hdwf, channel, 1)
dwf.FDwfDigitalOutIdleSet(hdwf, channel, c_int(1))
dwf.FDwfDigitalOutTypeSet(hdwf, channel, DwfDigitalOutTypeCustom)
dwf.FDwfDigitalOutDividerSet(hdwf, channel, c_int(int(hzSys.value/1e8)))
dwf.FDwfDigitalOutDataSet(hdwf, channel, byref(rgdSamples), c_int(cBits))
dwf.FDwfDigitalOutRunSet(hdwf, c_double(cBits/1e8))
dwf.FDwfDigitalOutRepeatSet(hdwf, c_int(1)) # once

#LA Setup

dwf.FDwfDigitalInInternalClockInfo(hdwf, byref(hzSys))
#dwf.FDwfDigitalInTriggerSourceSet(hdwf, trigsrcDetectorDigitalIn)#Use Below as per Attila@Digilent
dwf.FDwfDigitalInTriggerSourceSet(hdwf, trigsrcDigitalOut)
dwf.FDwfDigitalInTriggerSet(hdwf, 0,0,0xFFFF,0xFFFF);
dwf.FDwfDigitalInTriggerAutoTimeoutSet(hdwf, c_double(10.0));
dwf.FDwfDigitalInDividerSet(hdwf, c_int(int(hzSys.value/1e8)))

# dwf.FDwfDigitalInSampleFormatSet(hdwf, c_int(2)) wrong
# !!! use 8 for 8bit, 16 for 16bit and 32 for 32bit samples
dwf.FDwfDigitalInSampleFormatSet(hdwf, c_int(8))

dwf.FDwfDigitalInTriggerPositionSet(hdwf, c_int(cSamples)) #As per Attila@Digilent
dwf.FDwfDigitalInBufferSizeSet(hdwf, c_int(cSamples))

#LA Enable
dwf.FDwfDigitalInConfigure(hdwf, c_bool(0), c_bool(1))

#PG Enable
dwf.FDwfDigitalOutConfigure(hdwf, c_int(1))

#LA Status Check
print ('LA Status Check')
while True:
	dwf.FDwfDigitalInStatus(hdwf, c_int(1), byref(sts))
	print ('STS VAL: ', str(sts.value))
	if sts.value == stsDone.value :
		break
	time.sleep(1)
print ('Acquisition finished\n')

#LA Read Sample Data
# !!! 1* for 8bit, 2* for 16bit, 4* for 32bit samples
dwf.FDwfDigitalInStatusData(hdwf, rgSamples, c_int(1*cSamples)) 

#Print LA Data
print('LA Channel-0 data: ', end="")
i = 0
for v in rgSamples:
	print((v&1),end="")
	i += 1
	if i%8 == 0:
		print(' ', end="")
print('\n')

#Device Close
dwf.FDwfDeviceClose(hdwf)

 

[Venkat]

Hi @attila,

It worked for me with the modified script provided by you.

I see the major change is :

1. LA samples are increased by 8 ( this should be go as i can ignore the last 8 samples when compare to the PG)

2. DigitalInSampleFormatSet to be c_int(8)

3. DigitalInStatusData data_array type

I have tried few times and all the time it worked. Next thing I need to increase the number of channels and repeat cnt etc.

Once again thanks a lot.

Regards,

Venkat

[Venkat]

Hi @attila,

I see the output of LA is matching only when set to certain frequencies.

1. (in my example above,  the freq is 1e8 = 100MHz) and output is matching:

Frequencey:  100000000.0
PG Channel-0 data: 10101110 11010011 10010010 11111111

LA Channel-0 data: 10101110 11010011 10010010 11111111 00000000

 

2. When the frequency is changed to 1MHz i.e. 1e6, output is not maching (looks like 1st sample is missing)

Frequencey:  1000000.0
PG Channel-0 data: 10101110 11010011 10010010 11111111

LA Channel-0 data: 01011101 10100111 00100101 11111110 00000000
 

3. When the frequency is changed to 1KHz i.e 1e3, output is not matching(again looks 1st sample is missng)

Frequencey:  1000.0
PG Channel-0 data: 10101110 11010011 10010010 11111111

LA Channel-0 data: 01011101 10100111 00100101 11111110 00000000
 

I have used the above modified script with different frequencies.

Could you please check at your end if possible by running the same script with 1MHz or 1KHz.

Thanks a lot.

Regards,

Venkat

 

 

[attila]

Hi @Venkat

Please use 32bit sampling and FDwfDigitalInSampleModeSet with 1 to have the first and last bits correctly captured like here: digilent_pg_to_la.py

[Venkat]

Hi @attila,

With your suggestions, now able to run at different frequencies ( > 1KHz).

Thanks a lot.

Regards,
Venkat