issue with design.txt file in xadc

[farhanazneen]

hello sir

  how to add design.txt please do let me know  when i run the behavioural simulation im not getting any output and my input values representing xxx as my design.txt is not being read please do let me know how to add design.txt  file in simulation. The below are the pictures of simulation & design.txt file. I just initialise the ip and after generation of output product i  got  2 design.txt files i dont know why.Please do let me know how to add design.txt such tht i can get correct output.Below is the attachment of initialised ip .

[jpeyron]

Hi @farhanazneen,

Looking at your previous posts it appears that you are using a Zedboard for this project. Here is a forum thread the discusses using the ps with the xadc Header that has a completed project for the Zedboard.  Here is a tutorial with the ps and xadc Header for the zedboard. Looking at your screen shots the first thing i see is you are selecting vaux0 through vaux3. If you are using the XADC header then these are the wrong channels. If you look at the zedboard reference manual here on page 26 it shows that vaux8 and vaux0 are the only channels available on the xadc header. The rest of the channels are connected to the FMC.  You will need a FMC mezzanine to access the other channels. 

thank you,

Jon

[farhanazneen]

Thanks for your reply sir @jpeyron  now i changed  the inputs of xadc header i gave input to Vp and Vn pins still design.txt is not readable please do let me know sir

[jpeyron]

Hi @farhanazneen,

Please attach a screen shot of your block design.  In your test bench are you giving the input initial values? Please attach your test bench.

 It looks like my previous post did not link the forum thread here that has the working zedboard xadc project done in Vivado 2016.4? If you do not have Vivado 2016.4 please download it (you can have multiple version of vivado installed) and see if you are able to run the zedboard_xadc project. 

thank you,

Jon

[farhanazneen]

sir @jpeyron this is my test bench and mainmodule  please do let me know why i couldnt get the proper output and the below are the warnings in vivado

xadc main.docx

xadc testbench.docx

[jpeyron]

Hi @farhanazneen,

Sorry about the late reply. Are you still having issues with the xadc?

thank you,

Jon

 

 

 

 

[farhanazneen]

@jpeyron sir 

hello 

xadc simulation issue never ends i was trying since past  3 weeks to simulate xadc with auxiliary input  vaux0 (zedboard xadc header pin) sinewave   but always stuck with the errors.Always there  is  warnings showing up  top module is not defined and undeclared parameters.Below is the attachments of main module , test bench and instantiation of ip. Please do let me know where iam making mistakes or else please provide me a main module & testbench  code with auxiliary input .

please provide me a mainmodule and testbench code with auxiliary input zedboard.

adc main.docx

adc testbench.docx

[jpeyron]

Hi @farhanazneen,

Looking a little closer it appears you are trying to simulate just the xadc ip core.  I did find a xilinx tutorial that does this for a different IP and Dev board but should be a helpful reference.  You might find it easier to simulate a project then just the IP Core. Here is an hdl xadc project for the Zybo that should be relatively easy to get working on the Zedboard.

thank you,

Jon

[farhanazneen]

@jpeyron  thanks for your reply sir my question is i simulated the xadc example project which is provided by xilinx without the auxiliary or differential inputs but my question is now i want to simulate xadc ip with auxiliary inputs in vivado simulator i wrote test bench too but im getting errors . could u provide me test bench for auxiliary input to simulate in vivado simulator without using sdk. The below is the attachment of xadc example project of  output without input i would like to implement same but with auxiliary input plz do let me know sir how to proceed.

[jpeyron]

Hi @farhanazneen,

Unfortunately, I do not have much experience simulating the XADC IP Core. I did find a tutorial here that should be helpful for you.  I would suggest to also reach out to Xilinx support here as well. 

thank you,

Jon