Zybo base system design

[Twoism]

Hello,
I've got some troubles while trying to fully understand the Zybo base system design. I need to replicate in my design (with Vivado 2015.4) the video part of the bsd, with the Axi display control ip. The design works but some points are not very clear to me:

I've notice that 2 different clock sources are feed to the PL: (FCLK_CLK0 @ 100 MHz and FCLK_CLK1 @ 150 MHz). What is the reason behind this? Isn't 100 MHz enough for the VDMA?

Why an Axi protocol converter is used? The design was build for an older version of Vivado (and ip library)?

Thanks


 

[JColvin]

Hi Twoism,

I have asked some of our applications engineers about this. They will get back to you here on the forum.

Thanks,
JColvin

[Bianca]

Hello,

Well first of all, the processor has the data bus HP0 and it uses it to read/write from DDR. VDMA is used to automatically display on the monitor, so the VDMA is connected to HP0 bus in order to r/w in DDR and the user needs to control the VDMA to access the memory. The AXI interface is used for the communication between the processor and the FPGA. You need it to control from the processor the modules utilized in the FPGA. 

Regarding the clocking, the 100MHz clock is created as standard for the ip cores we create to use in the project. In general the cores works on 100MHz. The 150MHz frequency is needed for the display. The HDMI needs a frequency of 148MHz and the data reading from DDR needs to be faster than the pixel frequency for 1080p resolution which is used for HDMI in this project.

The design, I suppose, was build for Vivado 2013.4

Best regards,

Bianca