wheezs Posted February 12, 2016 Share Posted February 12, 2016 hey i cant finger out how to get the internal clock to use in projects Link to comment Share on other sites More sharing options...
Commanderfranz Posted February 12, 2016 Share Posted February 12, 2016 Hi Wheezs, To access the clock for basic VHDL or Verilog designs you have to uncomment the clock line in your UCF file. That is, this line: #FPGA_GCLK NET "CLK" LOC = "N8" | IOSTANDARD = LVCMOS33; Then you use "CLK" to connect it in your design. You can find the master UCF file at reference.digilentinc.com/cmod_s6:cmod_s6 Kaitlyn Link to comment Share on other sites More sharing options...
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wheezs
hey i cant finger out how to get the internal clock to use in projects
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