MIPI to Digilent board, transfer rate, which boards work?

[timprepscius]

Greetings,

I'm not sure whether this question should go in the Sales board, or the FPGA board.  Here goes anyway:

 

I'm going to be using a FPGA to:

1. Receive a MIPI transfer from two distinct synchronized cameras.

2. Do some transformation, and output a final stream of same dimensions as single camera.

Total bit rate per camera = 1920(w) * 1080(h) * 90(fps) * 16(bit/pixel) = 2985 Mbps
Total input= 5970Mbs , total output 2985 Mbps

 

Which Digilent boards (Arty7 ArtyS7, ... etc) are capable of reading and writing this amount of information via IO pins?

 

Is it true that I the MIPI stream needs to be changed into an LVDS stream via a special chip:

Meticom: http://www.meticom.com/page2/page17/MC20901.html

or perhaps something like this: https://toshiba.semicon-storage.com/us/product/assp/interface-bridge/camera-interface.html

 

Do all the boards support the LVDS of the Meticom or the parallel of the Toshiba?  (I don't mean protocol of course, just bit transfer)

 

Thank you for any information.

[xc6lx45]

Don't get this wrong but something about your questions tells me this is a "high-risk" project...

Have you thought about getting two identical boards with a tested-and-tried camera interface with working drivers, and simply slapping them together with a ribbon cable e.g. 32 bits wide at 100-ish MHz clock frequency?

 

 

 

[elodg]

MIPI CSI-2 cameras use MIPI D-PHY for the physical transport layer. The D-PHY I/O standard is only supported by UltraScale+ I/O pins. Any other architecture needs some form of adaptation. The compliant solution is the Meticom D-PHY-LVDS translator. A compatible solution with a passive termination network is described in https://www.xilinx.com/support/documentation/application_notes/xapp894-d-phy-solutions.pdf

The compatible solution is in use on our Zybo-Z7 board's Pcam connector, which allows connecting one Pcam 5C camera module. It works up to the maximum data rate supported by the Pcam 5C, 672Mbps per lane, or 1344Mbps total.

Your data rate is a bit high. Check the per lane data rate, which will tell you whether the passive termination suffices or your will need an active level translator. In any case, getting those high data rates into the FPGA requires high-speed connectors, like the purpose-made Pcam or the generic FMC connector. FPGA datasheets will tell you the maximum data rate supported by LVDS transmitter/receiver depending on speed grades.

Some of our upcoming products will feature more than one Pcam connector. Check back for updates!

 

[xc6lx45]

Hi,

1 hour ago, elodg said:

The D-PHY I/O standard is only supported by UltraScale+ I/O pins. Any other architecture needs some form of adaptation.

an implemented passive adaptation can be found on Trenz' ZynqBerry:

https://wiki.trenz-electronic.de/display/PD/TE0726+TRM#TE0726TRM-CameraSerialInterface(CSI-2)

(see R48 / R49 in the schematic). Just for the record, this was what I had in the back of my head with the idea of "slapping two boards together".

Again, if you intend to build this from scratch without high-speed scope and lots of time, this does look like a high-risk project...