xadc data reception on high frequency

[train04]

Hii,

 

I had make a microblaze based  AXILite ADC design which transfer data through Ethernet via TCP protocol. in SDK I have modified  the echo server example code and transfer data frequently, till now everything works good, but when I am plotting this data using MATLAB tool ( ex. sine wave as input )  my real time graph for low frequency (upto 250 Hz) coming good but above this it became distorted and gives very unusual plot. 

I am attaching my plot and vivado design , please any one can suggest me what may be the reason for this or why I am getting like this output. 

please suggest  my mail ID IS : shubham.dwivedi@eiwave.com

 

 

[jpeyron]

Hi @train04,

could you post the sdk code you altered in the echo demo? Also what FPGA board are you using?

thank you,

Jon

[D@n]

@train04,

All of the charts you've shown above could easily be created under the appropriate circumstances.  Not knowing the conditions of your test, or what sort of response you were expecting, it'd be hard for me to comment.

Can you tell me what you were expecting to see and how/why the result you do see looks different from what you were expecting?

Dan

[train04]

Hii @jpeyron, @D@n

I am sharing the modified code ....

I am working on a ARTY board, giving input to A0 pin of J7 header as sine wave.

my ADC sampling rate is 1Msps, using an AXILite interface it is connected to microblaze core , by API ( XSysMon_GetAdcData(SysMonInstPtr, XSM_CH_AUX_MIN+4) , I am reading ADC data continuously  and for high speed I am sending it through Ethernet using TCP protocol and plotting it using MATLAB .but if sampling rate is same for  both high and low frequency why sine wave is not plotting correctly is graph when I go to KHz range. that is the only problem.

 

 

real_time_data_stream_plotting.m

main.c

echo.c

[D@n]

@train04,

All of the pictures you've given are consistent with a sampled sine wave.  I'm still not getting what the problem is.

The first thing I'm noticing from your discussion above is that it seems like you are jumping directly to an end-to-end test without first going through a series of separate component tests.  Have you broken the problem down into verifiable pieces?  If so, which pieces have you tested that you now have confidence in?

Perhaps this might help you understand what is going on: Whenever I build a data acquisition system like this one, one of my first tests is to create a test mode which replaces the input data stream (your sine wave) with a counter.  I would patch the counter in between the A/D and the CPU, using all of the XADC's interface pins but only replacing the output with a counter that increments on every new sample.  Since filtering would destroy the counter, I'd also bypass any filters--just not any downsamplers.  That allows me to quickly see if any data is dropped or repeated.  Only once the counter properly passes through my system do I return the data stream to the actual measured A/D input I want.

Can you tell if any data is getting dropped or repeated in your test setup?

That's test one.

Test two: You said you were sampling the data at 1Msps.  Tell me, are you receiving data at 1Msps?  This is usually a really easy test to do: Create two counters.  One counts from 0 to your system clock rate in Hz (minus one), the other counts data samples.  Make sure both counters clear at the same time, and record the number of data samples counted before clearing.  This second test is an important one because many students don't necessarily understand how to properly create and manage pipeline logic control systems, and a 1Msps data acquisition system depends upon such pipeline control systems.

See if those help,

Dan