TJ Posted February 11, 2016 Share Posted February 11, 2016 Hello, Does anyone have a VHDL example of how to store data in RAM by writing data into specific addresses and then reading data from specific addresses? I only need 8 or 9 bits if not then whatever you have available. Thanks, TJ Link to comment Share on other sites More sharing options...
hamster Posted February 11, 2016 Share Posted February 11, 2016 Have a look at http://hamsterworks.co.nz/mediawiki/index.php/MIC_and_AMP#delay_buffer.vhd Maybe it will help... Link to comment Share on other sites More sharing options...
TJ Posted February 11, 2016 Author Share Posted February 11, 2016 Thanks much that is really helpful. Do you have a recommendation for a test bench. Thanks much, TJ Link to comment Share on other sites More sharing options...
hamster Posted February 11, 2016 Share Posted February 11, 2016 Oh, if you want to get swamped with info, have a look at http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug901-vivado-synthesis.pdf from about page 97. It has examples on how to infer everything from single port ROMs to True Dual-Port Asymmetric Ram Write First RAMs in VHDL.... Link to comment Share on other sites More sharing options...
TJ Posted February 11, 2016 Author Share Posted February 11, 2016 Hamster, Ok thank you very much. TJ Link to comment Share on other sites More sharing options...
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TJ
Hello,
Does anyone have a VHDL example of how to store data in RAM by writing data into specific addresses and then reading data from specific addresses? I only need 8 or 9 bits if not then whatever you have available.
Thanks,
TJ
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