HLS clocking in Sysgen

[Omid]

Hi

I worked with FIR example in HLS tutorials of xilinx documents.

After successful  synthsizing and implementation of the c code, it is exported to sysgen environment.

Output of the block is correct if frequency sampling is 1 but if frequency changes, output is not valid anymore( it yields all zeros).

My question is how i can get a correct result in any given frequency sampling other than 1?

I couldn't upload project files due to size limit. It can be emailed if requested.

Thanks a lot.

[JColvin]

Hello @Omid,

Those of us here at Digilent have not worked with Vivado HLS and the associated tutorials by Xilinx, nor the sysgen environment, so you may get some better answers by posting on the Xilinx Forum.

Thank you,
JColvin