Verilog Question

[tnet]

Looking at this link: http://referencedesigner.com/tutorials/verilogexamples/verilog_ex_04.php

Essentially, this code does clock conversion. Why is this tutorial setting the WIDTH to be 3 and N=6? 

In their example, they say if I want to convert a 50 MHz clk to 5 Mhz, set N = 5. But why? What is the math/logic behind this so I can understand it.

The width (3), is the register size. Therefore it's 2^3 and can address up to 8 bits. That part makes sense.

Let me know.

 

[D@n]

@tnet,

You count up to five with the output negative, and then five more with the output positive.  The result is that it takes 10 cycles to return to the original state.

That said, the exercise has a serious problem with it: you don't want to use any clocks that have been generated in this manner within a @(posedge clk) or @(negedge clk) structure.  While what you have will toggle like a clock, it won't work like a true hardware clock due to the nature of the FPGA circuitry and tools that you are working with.  A better technique is to use what I like to call a clock strobe, with a circuit more like:

initial counter = 0;
always @(posedge i_clk)
if (counter == 9)
begin
      counter <= 0;
      stb <= 1'b1;
end else begin
      counter <= counter + 1;
      stb <= 1'b0;
end

Rather than toggling on the outgoing counter, following circuitry can then toggle based upon the (stb) value.

For more information, feel free to read this article--it also discusses doing this using fractional timing as well.

Dan

[xc6lx45]

>> Therefore it's 2^3 and can address up to 8 bits

not bits but the value goes 0..7. The original design needs a value of 6 so 3 bits is the minimum. Makes sense.

There is an implicit division-by-two in the negation of the output flipflop

clk_track <= ~clk_track;

so you need to set half the division ratio.

That said, DO NOT use this approach for creating an actual FPGA clock. Modern FPGAs are more complex and distinguish between dedicated "clock" signals and "information signals", with distinct routing resources. The clock divider would create a bridge from an information routing resource to a clock routing resource, and that gives you a warning in Verilog and a sub-optimal design.