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addyD

FFT without using Processor

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Hello,

       I need to take a 256 point FFT as a part of analyzing sine wave deviations. I have managed to make a functional ADC and now intend to use the output to get FFT. I was wondering if there were any simpler cases I could look to start with. Thank you.

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Depending on what you are after, a full FFT might not be appropriate. It also depends on your desired throughput rates (e.g. 48KS/s for audio, or 100MS/s for radio work).

'Srreaming' FFT functions are possible, where the oldest sample is removed from the calculation and the new sample added - but the data can't be 'windowed', which can be a problem.

Maybe if you told.us more.about the.end result you are after?

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2 minutes ago, hamster said:

Depending on what you are after, a full FFT might not be appropriate. It also depends on your desired throughput rates (e.g. 48KS/s for audio, or 100MS/s for radio work).

'Srreaming' FFT functions are possible, where the oldest sample is removed from the calculation and the new sample added - but the data can't be 'windowed', which can be a problem.

Maybe if you told.us more.about the.end result you are after?

Well sir @hamster,

        I am new to fpgas and am still figuring things out. The board I am using is zybo board and software is vivado. My project has me analyzing a sinewave of 50Hz. I am using the xadc in event mode driven sampling to sample at rate 1 Ksps. The part after this is where we are cluless. Our ultimate goal is to have FFT output in windows of 8-cycles. i.e [1 to 8] cycle - 256 digital samples, [9 to 16] - 256  digital samples, [17-24] - 256 digital samples and so on.....our job is to have the individual fft output of these 256 samples per window. We have no idea how the FFT core works and am reading the sheet  for fft logicore ip 9.0. As far as possible we want to avoid processors but if it can't be avoided we are fine with that. Thank you.    

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@addyD,

Let's see ... 1ksps / 50Hz = 20 samples per cycle.  8 cycles would then be 20*8 = 160 samples per FFT.  Are you really sure that's what you want?

FFT's work naturally at 2^N samples.  In order to get 160 samples, you'll need to stuff the FFT with zeros.  While this is doable, it's harder than to just fill the rest of your FFT with raw samples.

As for the window function, ... let's discuss that for a moment.  The FFT window function is a lowpass filter.  It needs to be by design, and all of the common window functions meet this criteria.  You want it to have a cutoff of roughly 2 frequency bins (i.e. a frequency response from -1/N to 1/N).  If you do that, then you will only ever need 50% overlap between your FFT's to avoid losing information.  Anything more than that is doing more work than you need to do.  The information you would get from 75% overlap could also be gained by just interpolating the FFT's outputs.

Now, back to your question.

  1. You have a working A/D.  Good start!  ... how do you "know" it's working?  Do you have a simulation for your A/D?  Have you managed to measure the samples from your A/D over an extended period of time?  Or can you only "see" the results of your A/D with a scope of some type?  Where you need to go next will depend upon your answers to these questions.  When building digital logic, I always recommend starting with a simulation, debugging your design in simulation, then and only then placing it onto your hardware.  Incidentally, you can find an example A/D simulator here that you might find valuable (or not).
  2. If you don't already have a means of doing so, you'll need a means of reading from that A/D.  I prefer a means I can use both within my simulation environment as well as within the actual hardware environment.  I discussed building something like that here, but your own needs may vary.
  3. Not sure if you can simulate the Xilinx LogicCore IP or not.  You should be able to simulate an FFT from this repository using Verilator  (I've done it).  There's also code to accomplish a window function within the repo, although you'll need to create the appropriate coefficients (hex file) describing that window function yourself.  The biggest problem with that FFT right now is that it'd be overkill: it only performs a complex FFT at this time, and most A/D's create real samples.  Still, it'd work ... it just might be more than you need and the simulator won't (really) care if it's overkill or not.
  4. You'll also need some means of getting the data out of your FFT and to somewhere you can examine it.  I discuss reading from an FFT using a Wishbone bus here, but you'll still need some sort of debugging bus to get you into the FPGA where you can read and write the Wishbone bus.

Hopefully this'll get you started,

Dan

 

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Thank you @D@n sir. I made a mistake we re sampling at 1.6KHz freq which gives us 32 samples per cycle and 8 cycles of that will give us 256 samples as fft input. I will go through all your suggestion. Thank you for speedy and detailed help!!

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