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tnet

Artix-A7 (CMOD-A7) System Clock Question

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Regarding the the board Artix-7 (CMOD-A7) - https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/reference-manual

The datasheet says there is an 12 Mhz clock input and says the input clock can drive MMCMs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. 

My question is, if I want an output clock signal to be 1 Mhz from this FPGA to some external hardware, would I have to do a clock computation (Convert 12Mhz to 1Mhz) in my verilog logic?

Just want to clear that out, thanks. 

Edited by tnet

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Hi,

If you're using the 12 MHz clock, it won't be a high-performance design anyway, no point in analyzing "below the noise floor". Just keep in mind that the general problem might be more complex than this simple solution.

Anyway, If I needed this 1 MHz clock generator myself in the lab and quickly, I'd use the clocking wizard to 8 MHz output freq.

Then...

reg [1:0] counter = 2'd0;
(*DONT_TOUCH="TRUE")reg tmp = 1'b0;
(*DONT_TOUCH="TRUE")reg theOutputReg = 1'b0;
always @(posedge clk8M) begin
    counter <= counter + 2'd1;
    if (counter  == 2'd3)

        tmp <= ~tmp;
    theOutputReg <= tmp;
end

This should be still better than (don't use this)
wire theOutput = (counter >= 3'd4); // with a 3-bit counter

Edited by xc6lx45

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Hi,

the above-mentioned "clocking wizard" is your interface to a hardware unit on the FPGA called "clock management tile" (CMT) (see here page 13).

The functionality is not easily modeled in "vanilla" Verilog, it's based on analog / mixed signal circuitry on the chip. What you can do is instantiate one unit (via the "clocking wizard") and use the Xilinx-provided model, ideally in the simulator Vivado provides. When this is working, you'll feed in a 12 MHz clock at the input and get an 8 MHz clock at the output.

At some point you'll run into the problem that the minimum output frequency of said hardware unit is 4.688 MHz, it won't give you 1 MHz. That's where my previous post starts: Use the CMT to go from 12 MHz to 8 MHz (CMT / MMCM-internally: by going from 12 MHz to 768 MHz = multiply by 64, then down to 8 = divide by 96). My post gives you the missing division by 8. And again, the disclaimer, this is not a standard design procedure for reasons I won't go into. It'll get us from A to B but we're driving on the wrong side of the road...

 

Edited by xc6lx45

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On 7/10/2018 at 5:23 PM, xc6lx45 said:

Hi,

If you're using the 12 MHz clock, it won't be a high-performance design anyway, no point in analyzing "below the noise floor". Just keep in mind that the general problem might be more complex than this simple solution.

Anyway, If I needed this 1 MHz clock generator myself in the lab and quickly, I'd use the clocking wizard to 8 MHz output freq.

Then...

reg [1:0] counter = 2'd0;
(*DONT_TOUCH="TRUE")reg tmp = 1'b0;
(*DONT_TOUCH="TRUE")reg theOutputReg = 1'b0;
always @(posedge clk8M) begin
    counter <= counter + 2'd1;
    if (counter  == 2'd3)

        tmp <= ~tmp;
    theOutputReg <= tmp;
end

This should be still better than (don't use this)
wire theOutput = (counter >= 3'd4); // with a 3-bit counter

Hi, Thanks for the reply.

Regarding the clocking wizard to to output an 8MHz freq. Is this clocking wizard within Vivado I'm assuming? If so, then that makes sense.

What about if I'm purely testing this on ModelSim, therefore there is no clocking wizard and it would be purely down in verilog, no?

Is there a mathematical way I can see this being shown, that tells me type bit-counter to use, etc, and replicating it in verilog.

Other than that, this makes sense. Thanks.

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@tnet,

I have to deal with this often, although not with ModelSim.  I do most (all?) of my simulation using Verilator.  Verilator works using open source IP, and does not simulate Xilinx hard cores--like the result of the clocking wizard.

Here's how I handle it.

First, anything that I can simulate, I place into a main module.  "main" and everything that cannot be simulated goes into a "toplevel" design module.  You can see an example of this in my CMod S6 project.  Inside the toplevel.v file there's a reference to a digital clock management component, as well as the main simulatable core I called busmaster.  Within busmaster (i.e. the "main" simulatable file), everything is pure verilog.  That pure verilog incidentally knows nothing about the 8MHz clock input, but only the 80 MHz system clock.

Incidentally, the fact that I kept building projects to the same form was one of the motivations behind building AutoFPGA.  You can read about that project here.

Hope that helps,

Dan

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14 hours ago, D@n said:

@tnet,

I have to deal with this often, although not with ModelSim.  I do most (all?) of my simulation using Verilator.  Verilator works using open source IP, and does not simulate Xilinx hard cores--like the result of the clocking wizard.

Here's how I handle it.

First, anything that I can simulate, I place into a main module.  "main" and everything that cannot be simulated goes into a "toplevel" design module.  You can see an example of this in my CMod S6 project.  Inside the toplevel.v file there's a reference to a digital clock management component, as well as the main simulatable core I called busmaster.  Within busmaster (i.e. the "main" simulatable file), everything is pure verilog.  That pure verilog incidentally knows nothing about the 8MHz clock input, but only the 80 MHz system clock.

Incidentally, the fact that I kept building projects to the same form was one of the motivations behind building AutoFPGA.  You can read about that project here.

Hope that helps,

Dan

Hi @D@n, the code below shown in your clocking management. The DCM_SP and ".CLKDV_DIVIDE, .CLKFX_, etc..." are usable in the Artix-A7 Cmod-A7 35T? I didn't see these in the datasheet, so wasn't sure if I'm able to define these.

 

	//
	// Clock management
	//
	//	Generate a usable clock for the rest of the board to run at.
	//
	wire	ck_zero_0, clk_s, clk_sn;

	// Clock frequency = (20 / 2) * 8Mhz = 80 MHz
	// Clock period = 12.5 ns
	DCM_SP #(
		.CLKDV_DIVIDE(2.0),
		.CLKFX_DIVIDE(2),		// Here's the divide by two
		.CLKFX_MULTIPLY(20),		// and here's the multiply by 20
		.CLKIN_DIVIDE_BY_2("FALSE"),
		.CLKIN_PERIOD(125.0),
		.CLKOUT_PHASE_SHIFT("NONE"),
		.CLK_FEEDBACK("1X"),
		.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
		.DLL_FREQUENCY_MODE("LOW"),
		.DUTY_CYCLE_CORRECTION("TRUE"),
		.PHASE_SHIFT(0),
		.STARTUP_WAIT("TRUE")
	) u0(	.CLKIN(i_clk_8mhz),
		.CLK0(ck_zero_0),
		.CLKFB(ck_zero_0),
		.CLKFX(clk_s),
		.CLKFX180(clk_sn),
		.PSEN(1'b0),
		.RST(1'b0));

 

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No, sorry, those are specific to the Spartan 6 used in the CMod S6.

If you want to use this type of primitive within your Verilog code, the series 7 versions are MMCME2_BASE or PLLE2_BASE.  (There are also advanced versions of each.)  You can find these two hardware elements defined in summary in the 7-series libraries guide, and in detail within the 7-series FPGA clocking resources user guide.  Should you choose to use the wizard, the code generated will just simply configure one of these elements.  Personally, I find it easier to just include the elements within my code to properly configure the clocks.  The problem with that approach is that it isn't as friendly for beginners, despite being more powerful for the user of the elements.

Dan

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