I am running through the ARTY OOB GPIO demo, and have had no end of issues (Had to install older 2015.2 to even get the tcl to load, file locations, etc).
I did get the batch file to run the FPGA load, and can see the terminal responses. Looks same as the built-in demo, except loaded from the USB. So that's all good.
Want to play with SW changes, so went on to getting the design loaded....
Eventually got the demo to page 21 of the manual....
- Design is read in now OK
- have block diagram, XDC, etc
However, when I attempt to generate a bitstream, it complains at the synth stage:
[Vivado 12-1411] Cannot set LOC property of ports, Terminal qspi_flash_sck cannot be placed on L16 (IOB_X0Y43) because the pad is already occupied by terminal qspi_flash_sck_t possibly due to user constraint ["c:/users/steve/desktop/Arty_stuff/7A35T_Arty_OOB_GPIO_demo_VIV2015_2/ipi/project_1/project_1.srcs/constrs_1/imports/xdc/design_1.xdc":9]
To be clear, I haven't changed anything. This is just straight out of the demo.
I did try to comment out the pin L16 constraint to see what happens. It got further.... synth and implementation completes, but it then falls over at the bitstream stage.
Do I have the wrong board definition file (or version) or something?
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SteveD
Hi,
I am running through the ARTY OOB GPIO demo, and have had no end of issues (Had to install older 2015.2 to even get the tcl to load, file locations, etc).
I did get the batch file to run the FPGA load, and can see the terminal responses. Looks same as the built-in demo, except loaded from the USB. So that's all good.
Want to play with SW changes, so went on to getting the design loaded....
Eventually got the demo to page 21 of the manual....
- Design is read in now OK
- have block diagram, XDC, etc
However, when I attempt to generate a bitstream, it complains at the synth stage:
[Vivado 12-1411] Cannot set LOC property of ports, Terminal qspi_flash_sck cannot be placed on L16 (IOB_X0Y43) because the pad is already occupied by terminal qspi_flash_sck_t possibly due to user constraint ["c:/users/steve/desktop/Arty_stuff/7A35T_Arty_OOB_GPIO_demo_VIV2015_2/ipi/project_1/project_1.srcs/constrs_1/imports/xdc/design_1.xdc":9]
To be clear, I haven't changed anything. This is just straight out of the demo.
I did try to comment out the pin L16 constraint to see what happens. It got further.... synth and implementation completes, but it then falls over at the bitstream stage.
Do I have the wrong board definition file (or version) or something?
Thanks
Steve
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