CLK not lvcmos18

[Valentin]

HI.

I through clocking wizard created clock = 50 MHz. But oscilloscope give me amplitude lvcmos12 instead lvcmos18. Constraint is set to lvcmos18, stregth = 12. When I set constant = 1, I measure voltage=1.8V. When change stregth, amplitude is also changed. Please tell me where I have a mistake?

[xc6lx45]

Hi,

FYI: you couldn't change the output drive voltage through programming. It's set by the bank's supply pin.

Is your scope loading the signal with 50 ohms - there's a "50 ohms" icon on the screen - and / or did you configure the scope impedance correctly for your probe?

You observed that it depends on drive strength, so it looks like you're accidentally loading the FPGA output...

 

[Valentin]

1 hour ago, xc6lx45 said:

Hi,

FYI: you couldn't change the output drive voltage through programming. It's set by the bank's supply pin.

Is your scope loading the signal with 50 ohms - there's a "50 ohms" icon on the screen - and / or did you configure the scope impedance correctly for your probe?

You observed that it depends on drive strength, so it looks like you're accidentally loading the FPGA output...

 

What drive strength i need use?

[xc6lx45]

Any drive strength (just pretend the option does not exist).  It's not sensitive, more related to the slew rate than the level. Unless you know otherwise, it's unlikely to fix your problems...

One example where you'd reduce drive strength is to limit emissions and coupling, use the slowest possible signals that get the job done.

Your signal looks clean, the edges are pixel-perfect. I'd look at the scope, not the FPGA.