Jump to content
  • 0

Appeal for a Nexys4DDR project example using MIG in ISE


Anding

Question

Hello,

I've asked a few separate questions about getting implementing the Xilinx MIG on the Nexys4DDR using ISE 14.7.  Unfortunately I am still struggling with it.

I wondered is there anyone, perhaps at Digilent or elsewhere, who has successfully implemented MIG in a Nexys4DDR design using ISE?  If you have, would it be possible for me to take a look at the code where you instantiate the MIG and the (final and likely modified) MIG-generated timing constraints file that you are using?  This would really be a great kindness.

Question to Digilent here: I notice that all of your Nexys4DDR projects that use the DDR memory were migrated to Vivado before being released.  Is the implication here that a Nexys4DDR design using MIG in ISE, is really not feasible? 

I'd much appreciate any responses : so I can either get inspiration from your successful code (which would be greatly appreciated :-) or acknowledge defeat in ISE and at least stop losing time on this issue.

Many thanks

Link to comment
Share on other sites

9 answers to this question

Recommended Posts

Hi Anding,

I can't speak towards the feasibility towards using the MIG in ISE. I would think it's possible considering that the migration guide and the SRAM-DDR component pages were originally written for ISE, but as Xilinx only supports the Vivado toolset now, I don't think Digilent will do many (if any) ISE based projects anymore. I'll ask our applications engineers though and see if they happen to have something available though.

Thanks,
JColvin

Link to comment
Share on other sites

Hi Anding,

We've been struggling with the MIG in ISE as well, and it's proven to be too difficult to implement. I suggest you work with Vivado, as it has updated licenses, better IPs, and is more user friendly than ISE. We are no longer providing support for the ISE toolset, so continued use of ISE may prove to be increasingly difficult as you run into more walls such as this one.

I hope you understand and wish you the best of luck with Vivado if you choose to use it.
Andrew

Link to comment
Share on other sites

Hello Anding,

I would highly suggest moving to Vivado.  It is a small jump but I found it to be a very similar workflow.  I have never tried using the MIG in ISE.  I'm sure it is possible but obviously isn't easy.

On top of that, we have examples of using the MIG on the Nexys4DDR in Vivado.

Best of Luck,

Marshall

Link to comment
Share on other sites

Hi Marshall, Andrew

Thank you very much for your post.  I believe you are right that spending too much time with MIG in ISE is not really productive.  

I've actually migrated my project to Vivado as a standby but after a couple of months my personal view is that, apart from the MIG issue, ISE is still a nicer tool for a hobbiest the like myself.  I'll cite some examples:

Vivado doesn't actually support Windows 10 - wizard file dialogs simply crash out (including the MIG wizard!).  ISE works fine in Windows 10 with a simple fix

Its easy to create instantiation templates and testbenches with a "right-click" in ISE, but the TCL tools in Vivado don't work especially well

Vivado doesn't recognise the VHDL method of instantiating entities without a prior component declaration (inst: entity work.EntityName), so either you create (and continually modify) component declarations for all entities or use a ugly workaround by setting all files as global includes.

The Vivado simulator is much faster when it is running but takes a lot longer to get started than ISE, so not so good for rapid iteration and testing

SmartXplorer is very helpful in closing timing, but it's gone in Vivado

The other option is to manage without the MIG and develop a DDR2 interface in VHDL.  How feasible would you judge that this is?

thanks again, Anding

Link to comment
Share on other sites

I've asked around because I have no experience writing my own interface and have been told that it is incredibly difficult to do, but not impossible. It was suggested that you could use the SRAM to DDR Component to interface with the DDR memory on the Nexys4 DDR. The component allows projects designed for the Nexys4 to be easily ported to the Nexys4 DDR, but in your case you can simply use it as a memory interface.

I wish you the best of luck working in ISE on Windows 10. You make some valid points from a hobbyists perspective on why ISE is a nicer tool. 

Hope this helps,
Andrew

Link to comment
Share on other sites

You bring up some valid points.  I guess I just have gotten use to not having the instantiate templates and I primarily use Verilog so I didn't notice the VHDL issue.  I didn't know that ISE was working in W10.  is it the same fix a that allowed ISE to work in W8?

I agree with Andrew.  Use the SRAM to DDR component.  It will save a lot of time.

Best of Luck,

Marshall

 

Link to comment
Share on other sites

Hi Marshall,

Yes, ISE will work fine in Windows 10 with that same rename-the-lib-files fix as Windows 7/8.

Thank you for the suggestion on the SRAM to DDR component.  I found reviewing the code very instructive.  But of course that component also relies on instantiating a MIG if it is to run in hardware.

For my own project I have been able to write a small module to interface directly with the MIG's user interface and which will give me a burst mode and has some arbitration for multiple ports.  It simulates successfully, but igetting the MIG itself through place and route which has been the difficulty!

Thanks again for all of your suggestion.  I'm sure I'll be posting here again.

 

Link to comment
Share on other sites

Archived

This topic is now archived and is closed to further replies.

×
×
  • Create New...