I've asked a few separate questions about getting implementing the Xilinx MIG on the Nexys4DDR using ISE 14.7. Unfortunately I am still struggling with it.
I wondered is there anyone, perhaps at Digilent or elsewhere, who has successfully implemented MIG in a Nexys4DDR design using ISE? If you have, would it be possible for me to take a look at the code where you instantiate the MIG and the (final and likely modified) MIG-generated timing constraints file that you are using? This would really be a great kindness.
Question to Digilent here: I notice that all of your Nexys4DDR projects that use the DDR memory were migrated to Vivado before being released. Is the implication here that a Nexys4DDR design using MIG in ISE, is really not feasible?
I'd much appreciate any responses : so I can either get inspiration from your successful code (which would be greatly appreciated :-) or acknowledge defeat in ISE and at least stop losing time on this issue.
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Anding
Hello,
I've asked a few separate questions about getting implementing the Xilinx MIG on the Nexys4DDR using ISE 14.7. Unfortunately I am still struggling with it.
I wondered is there anyone, perhaps at Digilent or elsewhere, who has successfully implemented MIG in a Nexys4DDR design using ISE? If you have, would it be possible for me to take a look at the code where you instantiate the MIG and the (final and likely modified) MIG-generated timing constraints file that you are using? This would really be a great kindness.
Question to Digilent here: I notice that all of your Nexys4DDR projects that use the DDR memory were migrated to Vivado before being released. Is the implication here that a Nexys4DDR design using MIG in ISE, is really not feasible?
I'd much appreciate any responses : so I can either get inspiration from your successful code (which would be greatly appreciated :-) or acknowledge defeat in ISE and at least stop losing time on this issue.
Many thanks
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