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SteveD

Pmod OLED rgb and ARTY

Question

Kind of new to the world of FPGA tinkering.

Just bought an ARTY board and the OLEDrgb pmod.

Struggling to find some verilog code for the SPI driver, together with some simple demo that I could use with Vivado, perhaps a simple MicroBlaze code snipet that drives the display. I could then use this a base going forward.

Does anyone recommend anything here?

Thanks
Steve

 

 

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Hi Steve,

I know I would certainly like some cool FPGA projects for various Pmods; I know there are plans to do this in the near future. In the meantime, I'll ask some of our applications engineers to see if they have helpful resources that they know of.

Thanks,
JColvin

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Hello Steve,

I'm working on a PmodOLEDRGB project for microblaze right now. I will let you know when it is complete. In the mean time you might try checking out the PmodOLED example code on the Wiki. I haven't looked into it, but I think they should work somewhat similarly.

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Hey Tom, thanks for the response. Looking forward to your uBlaze project.

I will also check out the Pmod OLED as you suggest.

Not sure if you were involved in the other uBlaze project for Arty (i.e. the OOB GPIO/LED example) but I had an issue with that one. Basically I can't get it to synthesize to due issues with L16 pin. No idea what the issue is. I entered another thread on this. I did however manage to just use the bit file for the design and make various changes with the SDK to generate the ELF, and then do the merge with the SDK, both directly to FPGA and also by overwriting the Flash image. However, after trying various changes, I still can't get the design (from the project files with no change) to get through synth.

Thanks
Steve

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Hi Steve,

I actually didn't know that project existed, but there are a couple others who are having the same problem. That project was made by Avnet. I checked it out and found that they manually constrained the sck pin on the QSPI bus. This can be fixed by removing the qspi_flash_sck from both the constraints file ("design_1.xdc") and from the block design. I'm pretty sure this was a bug with the old board files, so redownload the newly uploaded boardfiles before you try this fix. You can find the latest boardfiles here.

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Which MicroBlaze project are you referring to?

For the OOTB GPIO/LED project, I did the changes that Tom suggested above, and that worked. Seems strange that the original Avnet design had an error that means the design won't go through synth. I did use the "new" board files too.

As for the topic of this thread, the OLEDrgb PMOD....

No nothing new here. I have precisely zero information on the chip that drives the RGB panel, so hard to know what to do. They give a power up and power down sequence, but nothing in terms of how/what to drive the SPI with. No registers, no nothing. 
So the module I purchased from Digilient is pretty much useless right now. Wasted $29.99. Which came to almost $45 Canadian with shipping/tax/fx/etc. That kind of money would have bought me a beer at a Canucks game!

Eagerly awaiting something from Tom that he mentioned above. Some example project with driver code for that display.
It does seem a bit strange that Diligent would sell something that no-one can actually use. I even tried to get a data sheet directly from the chip manufacturers in HongKong (Solomon Systech SSD1331) but no response.

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Hi SteveD,

I sincerely apologize that this thread has gotten dropped by our team, I'll make sure that Tommy gets back to you on this. 

As for the PmodOLEDrgb, I found the datasheet for the SSD1331 available from Adafruit here. However, like the PmodOLED this datasheet is rather difficult to decipher, so I would personally look at the Cpp and header file for the PmodOLEDrgb (available to download from it's Resource Center here in the MPIDE zip file). I agree that this is not the most helpful in terms of developing a MicroBlaze project, but at the very least will give you some insight into the initialization procedure and the needed SPI commands to send the display controller.

Thank you for your patience,
JColvin

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Hey guys,

I'm sorry it's been a while. I do have a working microblaze project right now. It uses a new pmod interface that I've been working on. It's still in the works, but I'll upload it and update the board files on the Github to add support. I'll let you all know when it is uploaded, probably an hour or so

Edited by tom21091

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Alright, the updated board files and library files are up on Github. I have attached a project for Arty that uses the PmodOLEDrgb and the new Pmod interface. It must be generated in Vivado 2015.4. To generate it, first unzip it, then open Vivado 2015.4. In the tcl console, type "cd <path to the PmodOLEDrgb/proj folder>". Then type "source ./create_project.tcl".

Hope this helps!

PmodOLEDrgb.zip

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Hey Tom,

Excellent. Thanks for all this work. I'll see if I can get something going. I have the design read into Vivado, and just trying to understand what you did.

Last night I also coded up a simple SPI statemachine to just try to get something (anything) written into the PMOD. I mean pure Verilog with no uBlaze.
If I could initialize the board and then draw a red box and a green line I would have been happy. Was just about to try all that before you sent this better way forward:-)

I see some big clocks in there: 200MHz and other odd ratios....

Thanks
Steve

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Hey Tom.

I tried this project and I have had some issues. To be honest, its more likely SW "newbie" issues from me than anything else. I'm a HW guy a heart, not really an embedded SW guy. The Xilinx SDK kind of scares me alot. I was hoping I could step through a similar previous example (the OOTB GPIO demo) to see if I could figure out how to get the SDK to work. I managed this with the OOTB demo, but I think I'm lost with this one. I did the Vivado build and got a bit stream, and exported it for the SDK. That was OK, kind of. Co-incidently I always get timing violations (4 of them) with the uBlaze, but this is not the issue. Like I said I can generate the bit-file.

My biggest issue is within the SDK, I could never seem to get it to successfully program the FPGA, using the system_wrapper BIT/MMI files, together with the ELF that I believe comes with the project (using this instead of bootloop). It "runs" but nothing on the display.

And I'm not sure how I suck in the newly created bitfile, the C-code, etc. Its all a bit black magic to me. Setting up the right repositories maybe.

BTW as an aside, I did go and right up a simple state machine in Verilog to try and send the SPI commands to the display. No MCU, just a few state machines.
I must have some sequencing issue, as the display flashes briefly, but no red line appears as planned. Oh well.

Are you planning on adding some step by step instructions for the SDK? Just wondering.

Thanks
Steve

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Hey Steve,

Sorry it's been a while, I'm taking a vacation right now and won't be back in til next week. It's a bit unsettling that you're getting timing violations as this might be why your micro blaze design isn't working, but who knows at this point. The weird clocks are for the DDR memory actually. The part that's on the arty needs a 166.67 MHz clock with a 200 MHz reference clock. Have you tried completing the getting started with micro blaze tutorials on our Wiki? They might help with getting familiar with the work flow. I will be putting together a tutorial for the new Pmod interfaces when we release then, but it's still pretty early. 

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Hey Tom,

I got Arty Board. I respectivly did arty wiki. I'm try to reach pmods with your ips. However when i route the pmod ip, mig, microblaze freq. conflicts occurred. Like that
"[BD 41-238] Port/Pin property FREQ_HZ does not match between /PmodACL_0/ext_spi_clk(50000000) and /mig_7series_0/ui_clk(83250000)"
"[BD 41-238] Port/Pin property FREQ_HZ does not match between /PmodGPS_0/s_axi_aclk(100000000) and /mig_7series_0/ui_clk(83250000)"

Is there necesseary to use mig for clocking (wont use ddr3) with microblaze ?  My design is attached. I need handle with spi and i2c.

Thanks,
Emre

new_design.pdf

Edited by mitokondri

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Hi Emre,

I just uploaded a new version of the IPs that don't have input frequency parameters, so they should work with whatever input frequency you give them. I think the ext_spi_clk still needs an input frequency of <50MHz to work though. 

You can create new clocks by double clicking the MIG IP block. Click "Next" until you see "Select additional clocks". Check the box and choose the clocks that you need. Then click Next Next Next Next,Validate, OK, Next, Next Next Accept, Next, Finish. It's a bit of a pain, but that's the MIG.

Hope this helps!

Capture.JPG

Edited by tom21091
Added picture

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Tom pmod_acl worked very well, so thank you :)  , i have found small errors
1-pmod_gps c sources. "NMEA mode;" defined and bool GPS_getData(PmodGPS* InstancePtr) and its return bool in the function different types. I have been change bool to NMEA.

2- When i use gps, some of included libraries are missing, like #include <stdlib.h>,#include <stdio.h>, #include <string.h> i download and added that libraries. little errors, Actually it is not so important to use.

3- I need use own i2c(j3 header) and spi(j6 header), when i run prepared code which name is test_perip, all of peripherals passed. But when i looked my osiloscope and logic analyzer did not trigged.(clocks, data ways) My coded i2c code was attached. If you got any simple i2c. I need them. 

again thank you,
Emre

iic_test_code.c

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Hi Emre,

The PmodGPS library is kind of in shambles right now, but I'm working on fixing it up in the next week.

As for I2C on the Arty, make sure you are setting the "I2C Pullups" board component high. 

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In case anyone looks here for advice on using PmodOLEDrgb with Arty, I found (similar to SteveD's March 14 post) that I could get everything to upload to the FPGA and "run" but have nothing on the display (Vivado 2016.2 on Win 7).  After a bit of searching around, it seems the code was running, but the calls to usleep() were being macro'ed to millisecond sleeps not microsecond, so it was running 1000x slower than intended.  Dropping all calls to usleep() by 1000x made it run fine.

Edited by M_bipartitus

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