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Pmod Ad5


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Hello

I am using the Pmod AD5 to convert my analog signals from light sensor to be able to feed it into the fpga. Any one has an idea of how can i proceed? I tried by testing the AD5 by inputting an analog input but i cannot get to the digital output...any help would be highly appreciated..Thanks

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hi @jpeyron thanks for response

i'v included the PmodAD5 ip to my vivado  suite 2017.3 , when i tried to create a block design with the ip using microblaze processor  , on generating the bit stream i got some error message as attached in the image bellow.

ad5 block.PNG

error ad5.PNG

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I was able to complete a project using the nexys 4 ddr vivado 2017.3 and the Pmod AD5 ip core. You need to add the pmod ad5 ip core to the vivado library.  Then you will need to add the vivado library in projects->ip->repository. I followed this tutorial for the most part. on step 4.3 I also add a 3rd output clock at 50 MHz.. And on Step 5 I also add the Pmod AD5 and connected the 3rd clock output (50 MHz) to the ext_spi_clk on the Pmod AD5. Then the rest of the Vivado will be the same. In SDK you will add an empty application instead of the hello world. Then add the main.c from the examples folder in the Pmod AD5 folder. Program the fpga and then run the application.

cheers,

Jon 

nexys4_ddr_PmodAD5.jpg

nexys4_ddr_PmodAD5_1.jpg

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Hi @flexible111,

  At first glance i believe you need to add the pmod AD5 ip core to the vivado library in ip/pmods here and then add the vivado library to the project under settings->ip-> repository. On Monday I will make and verify a project using the Pmod Ad5 IP core using vivado 2017.3 and the nexys 4 DDR.

cheers,

Jon

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@JColvin

thank you very much ....i'l try and connect the ground of my load cell with that of ad5,......tho i used 1.5v battery to test at a gain of 1.....since at gain of 1 the ad5 can read voltage range +or- 2.5v...and i'm still getting the fluctuations.

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Hi @roman3017,

I have requested of our content team to add this IP; it will be a little while before it is there though since we will want to make sure it is formatted like all of our other IPs and make sure it gets verified by a second set of eyes before pushing it onto that platform.

Thanks,
JColvin

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Hi @flexible111,

What sort of load cell are you using and do you have the datasheet for it? Based on the data you are getting, I'm guessing that your load is cell is fairly sensitive and has some error or hysteresis associated with it, so the Pmod AD5 is detecting these small changes. The load cell and the Pmod AD5 should also share the same ground to help prevent any additional fluctuations in measurement as well.

Thanks,
JColvin

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On 13/12/2017 at 10:32 PM, JColvin said:

Hi @flexible111,

Whether or not you are doing something wrong depends on what you have attempted to do so far. Could you provide us some more information on what (presumably) HDL you have tried to implement, what board you are using, the .xdc file you are using, and what you are attempting to accomplish with the Pmod AD5?

Thanks,
JColvin

 

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Hi @flexible111,

I was not able to get Hamsters VHDL code to work but I was able to make a basic Pmod IP core to work. The IP core sets up spi communication and configures the AD5 to a gain of 1 and in differential mode with a1 and a2. It then converts the digital data into a voltage value and prints it through the usb uart to a serial terminal like tera term. I have attached the unofficial IP core below. I verified that it works with microblaze or zynq processors. While generating a bitstream using this IP core it will mention something about the pmod bridge. Click ok. This is not an issue. If you need a different configuration please use the Library JColvin posts on this forum as well as the data sheet here to adjust the IP core as needed.

PmodAD5_v1_0.zip

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i'm trying to use it with a load cell ....but before that, i want to connect a 1.5 battery to the ad5 AN1 to serve as my input, and i want to connect the the first 16_bit from the MSB i.e (24 downto 9)of samples declared on @hamster code to the 16bit led available on my nexys4 ddr, so having done that, thier was no output at the led, my expectation was to have the led's comming on indicating the binary sequence of the samples....using the code uploaded by @hamser.

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Hi @flexible111,

Whether or not you are doing something wrong depends on what you have attempted to do so far. Could you provide us some more information on what (presumably) HDL you have tried to implement, what board you are using, the .xdc file you are using, and what you are attempting to accomplish with the Pmod AD5?

Thanks,
JColvin

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@hamster ....i tried to tie the samples to LED so as to visualize how the conversion is going on...but i couldn't get any output.....meaning i'm yet to have the pmodad5 working .....please is their anythin that i'm getting wrong?..

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Hi @mramrahgu,

Going off of the fact that SPI typically is active when the chip select is low and inactive when the chip select is high. I believe that Hamster choose this value for the chip select "FF007FFFFFFFFFFF"  when initially configuring the IC with the data being transferred in the MOSI "00A5000000000000". It looks like some delays are being added for initial turn on and time for the registers to be set. You should look at the datasheet for the IC here for more information about what configurations you want the PmodAD5 to be set to.

cheers,

Jon

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Hi, JColvin, i'm here again.
I've been away from my project for some time but, i'm back now.
Well, it turns out that i can't check if it's working. I'm trying to set the most significant bit of the samples ( sample (23) ) to a led, because this bit tells me if it is above or bellow 0V. But when i fix the input into any voltave higher then 0V it dos not light.
And aswering your question, yes it is significantly above my noise level. My noise is about 20mV and my signal is 50mV with a duration of (100-80)us.
But right now, i dont have any clue of what to do.
Is there any other way i can comunicate with you ? email perhaps ?

Well, once again thanks for the help i'm really looking forward your answer.

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Hi,

Yes, your clock is currently too fast for the PmodAD5 to handle. You'll need to use a clock divider of some sort to get your clock rate down to 1 MHz much like hamster did earlier in this thread. There are several different forum posts explaining how you might do that (by hamster) herehere, and here. Note that PmodAD5 is limited to producing data only within a 4.7 Hz to 4800 Hz data rate.

The AVdd does not need to be exactly 5V. According to the first page of the datasheet, AVdd can be anywhere from 3V to 5.25V. You will need to make sure that the voltage source stays at a constant voltage, and 5V will work great for your application.

Yes, with that datastream, you may leave the other inputs (Ain3-Ain8) open and unconnected.

The output will describe the amplitude of the incoming signal. Looking at the manual, I agree that it is unclear what the output data represents; I'll work on amending that. When you read the output data, you will receive a stream of 24 bits of data. By default, the device is in bi-polar mode which is what you want considering that you have some "negative" spikes in your signal readings. From page 33 of the datasheet, the datastream will be equivalent to:

"Code = 2N – 1 × [(AIN × Gain/VREF) + 1] 

where: AIN is the analog input voltage. 
Gain is the PGA setting (1 to 128). and
N = 24."

So, with a default reference voltage of 2.5V, and a Gain setting of 32, we can determine what Analog input voltage is by rearranging the equation to be:

AIN = [( Code / 2N - 1 ) - 1 ] × VREF/Gain

As for working with the noise, now that I'm thinking it over again, there might be a way to determine if you are receiving noise or the signal. When you receive your desired signal, is it more or less guaranteed to be significantly above (or below, whichever the case may be) your noise level? If so, you would be able to take the values collected by FPGA and filter them in software to only report the values that are above your threshold level. 

However, if the signal value will be around the same voltage level as the noise, I do not think there would be a way for software or hardware to distinguish between noise pulses and signal pulses. 

I'm looking forward to seeing the pictures.

Let me know if you have any more questions.

Thanks,
JColvin

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Hello JColvin.
Once again, i must thank you alot for providing me such a help.

Well, i think my trigger is almost done, there are a few things that i want to check with you just to make sure that i'm not gonna blow up something.
The FPGA that i'm running only provides a clock of 66MHz or 40MHz, but i think i can convert the project that Mr Hammster developed for my clock, but do you think that this may be a source of some kind of trouble ?
My Avdd must be exactly 5V ?
I'll use the Ain1 and Ain2( i'll set this one to zero ) for my signal, but the others inputs, can i just let them open ? The stream of bit that you provided me already sets that my input will be only Ain1 and Ain2 ?
The output gonna be something that describes the amplitude of my signal, right ? i looked at the manual of the PMOD and i didnt understood it well, could you give me an example ? Digital electronic isn't my strong. And for the noise i told you, i dont need to erase it i just need to treat it and see if what i'm looking is a noise or my signal. So i'm already creating a logic for that treatment.
And one last thing, as you could see on the images my signal is almost like a " negative impulse " therefore the adc can read it the way we configured ?

As allways thank you a lot for the inestimable help.
Once my project is running i'll send you some pics of it.
Thanks .

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Hi 123244423,

You're free to ask any question you may have-- we've set up the Forum as a place for people to learn things that they don't already know about, so any "lack" of knowledge is not a detriment. 

You wouldn't actually need to worry about your FPGA needing to read the 50 mV signal directly. The PmodAD5 is an analog-to-digital converter (ADC), so it will take the 50mV and turn it into a series of digital bits (zeroes and ones) that correspond to the logic level low and high voltages that the FPGA uses and can easily read. Because of this, it may be easier to think of the gain factor in this ADC has increasing the resolution of the incoming analog signal (as opposed to increasing the amplitude of that signal) in terms of what kind of data we would be receiving from the PmodAD5.

However, as the gain factor that we select for the Programmable Gain Array internal to the Analog Devices (pg 32 of the datasheet) does increase the voltage of the incoming signal (as we would expect), it also correspondingly limits us to what kind of input voltages we can give to the chip so that we don't accidentally damage the chip or receive inaccurate data. According to the Analog Input specifications (bottom of page 5 of the datasheet), the differential input voltage that we apply needs to be between +/- Vref/gain. If we use the default reference voltage of 2.5V and set a gain of 32, this would allow us to apply a voltage anywhere from -78.125 mV to +78.125 mV without running into any issues. For the differential input, you can set 0V to the negative input and use the positive half of the pair as your actual input from the the Scintillation counter. 

A larger gain, such as the gain factor of 128, would limit us to 19.53 mV (2.5V divided by 128 = 0.01953 V = 19.53mV), which isn't quite large enough of a range to account for the potential 50 mV that you would be providing. A list of usable gain factors is given on page 28 of the datasheet and correspond to the last 3 bits in the datastream provided by hamster.

So the stream of bits we want to send out are:

0001 0000 0000 0100 0000 0001 0001 0000

The rest of his datastream should work for your application as well. He set it so that the pseudo differential measurement is used, which basically means that you would need to apply 0V to AINCOM on the PmodAD5 to match the 0V for the negative input as you suggested earlier.

When I said the "default" voltage, I meant that when that particular component is idling or not receiving any input of its own, did it have an output voltage of 0V. After reading up on your project, it sounds like this is the case. I apologize for not being more clear when I originally asked the question.

As for the noise from the thermionic emission, I have enough experience in the correct field to understand the idea of what your project is doing, but unfortunately I am not aware of a way to prevent or filter out this additional radiation. I guess ideally you would want to be in an isothermal environment, but that's easier said than done and beyond Digilent's realm of expertise.

Let me know if you have any more questions.

Thanks,
JColvin

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JColvin, first of all thank you for aswering my question so fast.


Well, actually it's not only the photomultiplier. It's a Scintillation counter ( https://en.wikipedia.org/wiki/Scintillation_counter ) . It produces this enormus noise becuse of the thermionic emission. I'm using this Scintillation counter as a trigger for a Particle Telescope, therefore i must find a way of ignoring this noise and use only the signal that a particle leaves when it reaches him. ( I took the liberty of attaching some photos of the sign produced by the passage of the particle, as I was adjusting it and placing it on a oscilloscope screen. )
Well for the diferential input, can't i set to 0V the negative input and use only the positive as a input ?
What do you mean whem you say  " "default" voltage of 0V " ? .
Wouldn't i need the gain of 100 ? Becuse i need my signal of 50mV( the particle signal ) to be read by the FPGA that i'm programming.
And for last, the only thing i need to change from the project Mr. Hammster developed is the stream of bits right ? To set the diferential input to work the way i want and for the gain i want. Right ?
And once again thank you for the invaluable help with these, and sorry for my lack of knowledge.
Thanks

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flcslR.jpg

 

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