Nexys 4 DDR with a new DDR2 chip

[Kopart]

We have 4 Nexys 4 DDR boards with the same "Rev C" revision.
I have compiled .bit file with MIG IP settings based on Digilent example "Nexys 4 DDR Xilinx MIG Project" in Vivado 2018.1

The fist two boards have MIRA DDR2 chip and DDR calibration complete successfully with this .bit file
The second two boards has ISSI DDR2 chip and DDR calibration fails with the same .bit file.

What are the MIG setting differences for these DDR2 chips? 
 

[JColvin]

Hi @Kopart,

We're taking a look into this; I learned that the Nexys 4 DDR can come with either DDR2 memory (as you found), but I don't have the ISSI version on hand so I'm asking to see if another one of my co-workers in a different office can test this out.

Thank you,
JColvin

[FPGA_LIFE]

Hi JColvin,

Is there any update on this issue?

I am also having the same issue with Calibrating DDR2 on Nexys4DDR board. Simulation works fine but as soon as I put the example design on board, I don't see DDR getting Initialized and Calibrated.

Thanks!

[jpeyron]

Hi @FPGA_LIFE,

We have confirmed that there could be either the MIRA DDR2 chip or the ISSI DDR2 chip on the Nexys 4 DDR. My understanding is that the ISSI is a drop-in replacement for the MIRA and should be configured the same.  We are searching for a Nexys 4 DDR that has the ISSI DDR2 on it to see if we can replicate the issue.  While we are doing this I was wondering if you have the board files installed? If so are you able to complete this tutorial?

thank you,

Jon

[FPGA_LIFE]

Thanks for the reply Jon.

Yes I have installed the board files but haven't completed this tutorial.

Will complete it and let you know.

 

Thanks!

[Kopart]

Hi Jon,

It will be good if you can generate approved ".bit" file with connected any "DDR2 Calibrating Done" LED or some debug probes.
I and @FPGA_LIFE can check it on our boards. 
It looks the best solution to exclude any our issues in Vivado synthesis workflow and to check the DDR2 chip calibration.

* Currently official Nexys 4 DDR support page doesn't have any pre-compiled FPGA firmware to verify the DDR2 chip.

[Bianca]

Hi @Kopart,

I'm really sorry for this issue. Can you please provide me the serial number for both boards and tell me what DDR they have. I would need also a high resolution picture of both chips, so I can be capable to take the manufacturing details from them. If you can't obtain a good picture, can you please tell me what's written on the chip?

Thanks,

Bianca

[Kopart]

1 hour ago, Bianca said:

Hi @Kopart,

I'm really sorry for this issue. Can you please provide me the serial number for both boards and tell me what DDR they have. I would need also a high resolution picture of both chips, so I can be capable to take the manufacturing details from them. If you can't obtain a good picture, can you please tell me what's written on the chip?

Thanks,

Bianca

Hi @Bianca,

Now we have three Nexys 4 DDR boards.
All these three boards have the same DDR2 chip label:

ISSI 1652
IS43DR16640C
-25DBL   K090
BNG137000V2 CHN 

But the new third board has working access to the DDR2 chip (calibration complete successfully) 

SN for these three boards:
1. DA6ECC0 - calibration complete successfully
2. DA6E850 -  calibration fails
3. DA6E83F -  calibration fails

[Bianca]

Ok, so just to be sure I understand. You said in your first topic that you have two Nexys4-DDR with MIRA DDR and two with ISSI. The ones with ISSI fail to calibrate.

And now you are telling that you have three boards, all with ISSI and one is working and two not.

Can you please provide me the .bit file?

Thanks,

Bianca

 

[Kopart]

1 minute ago, Bianca said:

And now you are telling that you have three boards, all with ISSI and one is working and two not.

Now we have three own boards with ISSI DDR.
Before we also have two loaned boards with MIRA DDR. It was used to start developing process before receiving our order for Nexys 4 DDR boards.
 

[Bianca]

@Kopart

Please try running this project  on your boards. I ran the project on boards with both ISSI and MIRA. The init calib pin is tied to Led0 so the LED should turn on as soon as the bit is loaded. The SDK project writes "hello world" to UART (9600 baud). 

 

Let me know how things turn out.

Nexys4DdrTest.zip

[Bianca]

Do you see any activity on UART leds? have you set correctly the com and the baud?

Eitherway, if the led is on, this means that the mig has calib.

Bianca

[FPGA_LIFE]

The Serial number for my board is DA6ECE4. It has ISSI DDR2 on it.

@Bianca, Looks like this zip file which you sent is corrupted, there were 800+ file errors. Please re-send it.

Thanks!

[elodg]

Check your internet connection, it works for me.

[Kopart]

17 hours ago, Bianca said:

@Kopart

Let me know how things turn out.

Nexys4DdrTest.zip

@Bianca

Thank you for this example project. 
All three boards show calibration success led with your pre-compiled .bit file.

I checked differences from my project. I connected sys_clock directly to the MIG IP and updated MIG input clock Frequency settings to 100Mhz.
Your project uses MCM to produce 200Mhz clock for MIG IP.
I updated my project in the same way. 
Now I see calibration on all three boards with my project.

[FPGA_LIFE]

@Blanca & @Jpeyron,

Thanks, I tried that tutorial and it seems to initiate and calibrate the DDR2 correctly. I looked at that tutorial previously but didn't try since there was a message on top saying this tutorial is obsolete.