Accessinng OCM memory from PL side

[Sridhar Prasath Aruppukottai Ganesan]

Hello all,

If  I need to access the OCM from PL side, do I need to create any specific blocks like AXI CDMA?? I need to store the incoming data from Axi Uartlite in OCM. How should i access it? What are the IP blocks required to connect in the hardware design? And What is the difference between OCM and DDR?? Which memory should i use to store the incoming data from the uartlite?

 

Note: I searched this question . And I didnt find any suitable answer related to my question. Please help me with this.

[Notarobot]

In my opinion the best answer you will find reading Xilinx ug585 document and searching Xilinx knowledge base.

In short OCM is intended for fast memory storage used by ARM or Microblaze processors. The fastest and simplest memory storage for PL is BRAM. You can read/write BRAM directly from both PS and PL. You can send blocks of memory from BRAM to OCM.

OCM is located on the Zynq chip while DDR is on separate chip. The size of DDR memory depends on the board manufacturer while the OCM memory size is always the same.