Nexys4DDR- Unusually high hold time violation detected

[Anding]

Hello,

I'm having trouble getting place and route (ISE) to meet timing on the Nexys4DDR.  The design is an update of an original design on the Nexys4 which met timing easily.  The only change is that a MIG7 has been substituted for the previous cellularRAM controller.

If it's not bad form and to avoid duplicate posts, may I link to where I have posted the issue on the Xilinx forum...

https://forums.xilinx.com/t5/Memory-Interfaces/MIG7-Unusually-high-hold-time-violation-detected/m-p/679727

Many thanks indeed for any suggestions

[JColvin]

Hi Anding,

It looks like you've gotten some helpful feedback from your Xilinx post already, but I've also asked some of our applications engineers about this to see if they have any additional thoughts.

Thanks,
JColvin

[Anding]

Hello JColvin,

May I ask for something that would help me a lot?  If you colleagues have an ISE project for the Nexys4DDR that includes a MIG and which has been successfully implemented in hardware, would it be possible to get a copy of the .UCF file with the timing constraints that the MIG generated?  It is found inside the MIG IP folder.

(I  don't mean the simple .UCF file that has the pin outs only; that is already on your website)

I could compare this known good version with what the MIGis generating in my design.  The engineers may actually have take the automatically-generated .UCF file and modified it to get the MIG to work.  A copy of that modified file would be especially valuable!

Many thanks indeed,

[cristian.ignat]

Hello,

In attachment you can find the UCF file used for DDR validation.

Regards, Cristian

mig_7series_v1_9.ucf