Vivado SDK can not import PmodNAV driver with Cmod A7

[Andris]

Hello!

I am started to create an application with Vivado 18.1 on Cmod A7 board with microblaze and 2 Pmod NAV IP. I downloaded these from Digilents's repository. After I successfully generated the bitstream from the hardware design, I exported and launched the Vivado SDK. I got the following error:

14:51:02 ERROR	: (XSDB Server)ERROR: [Hsi 
14:51:02 ERROR	: (XSDB Server)55-1550] Repository Directory C:/Users/L1/Documents/vivado_projects/project_x/project_x.sdk/szstem_wrapper_hw_platform_3/drivers doesn't exist in the disk

14:51:02 ERROR	: Failed to openhw "C:/Users/L1/Documents/vivado_projects/project_x/project_x.sdk/szstem_wrapper_hw_platform_3/system.hdf"
Reason: ERROR: [Common 17-39] 'hsi::open_hw_design' failed due to earlier errors.

14:51:02 ERROR	: Unable to create Hardware Specification Project with specification file: C:/Users/L1/Documents/vivado_projects/project_x/project_x.sdk/szstem_wrapper.hdf

After I googled a bit, this error seems for me to be related to this post . As I think, the Vivado failed to generate the hardware properly. Please give me some instruction to handle this error with the PmodNAV IP

My full Vivado project is available here and Thank You for the help.
 

[jpeyron]

Hi @Andris,

It might be easier to trouble shoot this issue if you were to attach a screen shot of your block design along with your wrapper and xdc file

thank you,

Jon

[Andris]

Thanks for your feedback @jpeyron

Here is my block design and my .xdc and I attached my system wrapper

My xdc file

## GPIO Pins
## Pins 15 and 16 should remain commented if using them as analog inputs
#PMODNAV1
set_property -dict {PACKAGE_PIN M3 IOSTANDARD LVCMOS33} [get_ports Pmod_out_0_pin10_io]
set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports Pmod_out_0_pin1_io]
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports Pmod_out_0_pin2_io]
set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports Pmod_out_0_pin3_io]
set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS33} [get_ports Pmod_out_0_pin4_io]
set_property -dict {PACKAGE_PIN H1 IOSTANDARD LVCMOS33} [get_ports Pmod_out_0_pin7_io]
set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports Pmod_out_0_pin8_io]
set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33} [get_ports Pmod_out_0_pin9_io]

#PMODBT
set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports Pmod_out_2_pin10_io]
set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports Pmod_out_2_pin1_io]
set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports Pmod_out_2_pin2_io]
set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports Pmod_out_2_pin3_io]
set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS33} [get_ports Pmod_out_2_pin4_io]
set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS33} [get_ports Pmod_out_2_pin7_io]
set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports Pmod_out_2_pin8_io]
set_property -dict {PACKAGE_PIN N3 IOSTANDARD LVCMOS33} [get_ports Pmod_out_2_pin9_io]

#PMODNAV2
set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports Pmod_out_1_pin10_io]
set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports Pmod_out_1_pin1_io]
set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports Pmod_out_1_pin2_io]
set_property -dict {PACKAGE_PIN T1 IOSTANDARD LVCMOS33} [get_ports Pmod_out_1_pin3_io]
set_property -dict {PACKAGE_PIN T2 IOSTANDARD LVCMOS33} [get_ports Pmod_out_1_pin4_io]
set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports Pmod_out_1_pin7_io]
set_property -dict {PACKAGE_PIN W2 IOSTANDARD LVCMOS33} [get_ports Pmod_out_1_pin8_io]
set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS33} [get_ports Pmod_out_1_pin9_io]


set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

 

szstem.v

[jpeyron]

Hi @Andris,

I can not see an issue with your design. What frequency are you giving the ext_spi_clk on the Pmod NAV? What did you configure the microblaze to? Here is a project done in Vivado 2018.1 that generates a bitstream. I just realized you were compressing the bitstream so you will have to re-generate bitstream with it compressed. 

thank you,

Jon

[u6113500]

Hi  @jpeyron,

I have the same issue. I found out that this error happens only when I am using more than 1 PmodNav IP in my design. With 1 IP it works fine.

Any ideas?

 

Thank you,

Anton

[jpeyron]

Hi @u6113500,

1) What version of Vivado are you using?

2) Please attach a screen shot of the TCL Console errors and the block design in vivado. 

3) What FPGA development board are you using?

4)  If the development board is made by Digilent are you using the Digilent board files?

Also once into SDK you will need to create another PmodNAV instance something like:

PmodNAV nav2;

and you will need to call all functions that use nav and make a second call to that function using nav2. So for example the NAV_begin() will need the xparameters for the second Pmod NAV. Something like:

NAV_begin ( // intialize the PmodNAV driver device

&nav2,

XPAR_PMODNAV_1_AXI_LITE_GPIO_BASEADDR,

XPAR_PMODNAV_1_AXI_LITE_SPI_BASEADDR

);

and for NAV_Init() it will be something like:

NAV_Init(&nav2);

Hope this helps!

 

thank you,

Jon

[u6113500]

@jpeyron,

1) Vivado & SDK ->2018.2;

2) Vivado design:

Vivado TCF:

SDK TCF: 

3) I am using Pynq Z1 board.

4) Board files are installed.

The same design works if I  use only one PmodNAV in my design.

[jpeyron]

Hi @u6113500,"

The SDK error shows that it is unable to find the hardware platform in the file location it is set to look at. I got the same error with "Vivado 2018.2" but not in Vivado "2017.4". I was not able to find this in the list known issues for Vivado/SDK 2018.2. I have reached out to our content team about this issue. Currently I would suggest using Vivado "2017.4".

thank you,

Jon

[u6113500]

Hi @jpeyron,

Do you have any updates?
 

Anton

[jpeyron]

Hi @u6113500,

We found that this issue in Vivado/SDK 2018.x occurs with some of our other IP Cores when using multiple of the same IP Cores in the same block design. We will address this issue on our next IP Core update. We have updated our Getting Started with Digilent Pmod IPs tutorial to reflect this issue. For now we suggest to use Vivado/SDK 2017.4.

thank you,

Jon