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Microblaze frequency


Billel

Question

Hey everyone

i'm using Basys3 board, i build my project based on Microblaze soft core. Usually project work with 100MHz frequency and it work perfect, now i'm trying to increase a Microblaze frequency to 200MHz, i have as frequency input the 100MHz sys clock and i set the output frequency to 200MHz (in the clk_wiz). when i run the implementation process i got this critical warning: 

[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.

Anyone have an idea how can i fix this error?

Currently am using Vivado 2015.1 (64 bit).

Best regards,

Billel

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It looks like the complexity of the design is such that it won't run at 200 MHz on the class of FPGA you are using. If you implement it at 100 MHz look at how much positive slack you have, you should be able to reduce the clock period by at least that much and try again.

e.g. if you have 2ns of slack when targeting a 100 MHz (10ns period) clock, you should be able to make it work at 125MHz (10ns - 2ns = 8ns period). You can do this a few times, until you only just meet timing. 

The only downside is that you can find yourself balanced on a knife-edge - a small change in the design might cause it to fail timing and error out again.

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