Multichannel data acquisition on Arty

[DrK]

Hey everyone

Brand new to FPGA, Vivado and all the "fun". I got an Arty board for evaluation with the hopes of porting a Labview based completed project into an FPGA based system. 

I need to acquire data from multiple 12 bit ADCs (48 total to be exact at 4MHz) at the same time and dump the data to the allocated memory spaces (on the DDR3) and then eventually read the data with an order and transfer it to a computer/SD card.

Looking at Vivado block interface, seeing MIG block really gave me the hopes but having no FPGA experience and half the tutorials not even working on my system is getting frustrating to even asses the project. What I'd like to know is if this is possible using this board. It doesn't have to be 48 ADCs, can be 24, or 12 for now but I need to be able to read them all at the same clock cycle and dump it to the RAM to be processed after the whole acquisition is done. 

 

Thanks in advance

[TommyK]

Hi DrK,

This is an interesting request. Are these ADC's external, or are you plannign on just taking measurements using the onboard hardware. The Arty has 10 ADCs onboard I believe. If you are trying to sample external ADCs at the same time, then I'm pretty sure it is doable. This sounds like a difficult project, especially with no FPGA experience. I'll have to ask around though.

[artvvb]

Hi DrK,

This sounds quite complex, but possible. I'm curious what you mean by the tutorials not working? Do you mean on the Arty,or on your PC? If the Arty, then this might just be a matter of the board file, XDC, or UCF, depending on what development environment you are using. First check that the tutorial is trying to do something that the Arty can do - for instance, it doesn't have an SD card slot - then use the Arty master XDC or UCF to translate the provided constraint file into something usable by the Arty.

I'm not sure what your ADC interface looks like, but it would be very difficult to read and dump in the same clock cycle, every clock cycle -- presumably you have a 25 clock cycle period to deal with the data though, with a base clock of 100MHz and an ADC clock of 4MHz. I believe that there is still a data bottleneck in writing to RAM, so you'd have to buffer the data in logic somewhere, then read in ADC data, possibly with burst writes.

Thanks,

Arthur