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kage-chan

Zybo custom IP core example

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Greetings everybody,

 

I recently purchased a Zybo (Zynq 7000 series application board), currently I am experimenting around with it a bit. This is the first time I am working with FPGAs, up to now I have only been working with other microcontrollers and cortex processors. 

While looking for reading material, I stumbled across this example, which shows how to create and use custom IP cores using Vivado. Since it is an official example from digilent and other examples worked without problems I though this one would be easy to follow, too.

Problem is, it doesn't work. I am following each and every step exactly as shown in the pictures and described in the text. After successfully generating the bitstream (no warnings/errors) and exporting it I run the SDK. The C code there compiles, too, I program the FPGA and launch the compiled ELF using GDB on the Zynq. Here I first have to turn off the "Run ps7_init" and "Run ps7_post_config" checkboxes in the run configuration, otherwise the elf won't run on the Zynq.

Now the ELF runs on the Zynq (or at least I hope so...), but nothing happens. Nothing at all. The LEDs are supposed to start pulsing, but they don't.

Does anybody have similar experience with the given example? Or can anyone tell me what's wrong or how to find out? I'm greatful for any help you might have to offer.

I currently am using Vivado 2015.4 (64 bit).

 

Best regards,

Daniel

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Hi Daniel,

I have asked some of applications engineers to take a look into this. They'll get back to you here on the forum.

Thanks,
JColvin

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Hi again Daniel,

I want to make sure your question gets answered as quickly as possible. Can you please post an image of your block diagram and your code. It's hard to figure out whats wrong without any code or error messages.

Kaitlyn

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Hey,

Thanks for the reply. I've attached everything I think is relevant or interesting, if I missed something please tell me. As I said, I just followed the linked tutorial. Maybe I did something wrong there.

The two Verilog source files are the ones from the custom IP block. The PNG shows the block layout which uses the newly created IP. The ZYBO_Master.xdc is the constrains file that goes with the block diagram. The HDL wrapper of the block diagram (not attached) is automatically created by Vivado. The C source file is the one I'm using in the SDK to program the Zynq's A9.

As a matter of fact it turned out I do not need to turn of the two said checkboxes in the SDK if I reset the whole system everytime I run the application and automatically have the FPGA reprogram. Just as a side note. Although it does not change the fact that my board (which is fully functional) does nothing at all when running this application.

Thanks for the help.

Greetings,

Daniel

ZYBO_Master.xdc

My_PWM_Core_v1_0.v

My_PWM_Core_v1_0_S00_AXI.v

main.c

LayoutDiagram.png

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Hi kage-chan,

I looked into it and found out it's a problem in Vivado 2015.3 and 2015.4. It looks like xparameters.h does not update the addresses for your custom IP core when you add it. So instead of giving it proper addresses, it defaults to Base addr 0xFFFFFFFF and High addr 0x00000000. Here is the Xilinx answer record for it. For a quick fix though, you can go into your Vivado block design, click the Address Editor tab, and copy the offset address there.

Capture.JPG.eb28beac359dd13095725688dda1

Then in SDK, replace the #define with the offset address. This should be the correct address of the first register in your component.

#define MY_PWM 0x43C00000

This should be fixed in future versions of Vivado.

 

Thanks,

Tommy

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Hi Tommy,

A thousand thanks to you, it wouldn't let me go. Now it finally works, thanks :D

But on the other hand, being stuck with this problem taught me so much about the Zynq, I'm kind of glad it happened.

Best regards,

Daniel

 

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