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Map problem on Nexys4DDR

Anding

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Anding Member

Anding

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Hello,

I am trying to implement a design in ISE using the RAM2DDR_REF_Component.  I get the following error at the MAP stage.  I used both the Nexys4DDR.ucf and the mig.ucf files to constrain the design.  Any help would be much appreciated.

ERROR:Place:897 - The following IOBs have been locked (LOC constraint) to the
   I/O bank 34.
   They require a voltage reference supply from the VREF pin(s) within the same
   I/O bank to be available.
   The following VREF pins are currently locked and can't be used to supply the
   necessary reference
   IO Standard: Name = SSTL18_II, VREF = 0.90, VCCO = 1.80, TERM = NONE, DIR =
   BIDIR, DRIVE_STR = NR
   List of locked IOB's:
    ddr2_dq<2>
    ddr2_dq<1>
    ddr2_dq<4>
    ddr2_dq<3>
    ddr2_dq<15>
    ddr2_dq<0>
    ddr2_dq<9>
    ddr2_dq<6>
    ddr2_dq<5>
    ddr2_dq<8>
    ddr2_dq<7>
    ddr2_dq<10>
    ddr2_dq<11>
    ddr2_dq<12>
    ddr2_dq<13>
    ddr2_dq<14>
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

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AndrewHolzer Prolific Poster

AndrewHolzer

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Hello Anding,

These errors are appearing because you are using the SSTL18_II iostandard, as you should be right now. This iostandard requires that you voltage reference which can be supplied internally as a setting in the RAM2DDR component. Double check to make sure that the Internal Vref is enabled.

Further, you don't need to include the mig.ucf to constrain the design as this is all handled by the mig itself.

Check the internal vref and remove the mig.ucf file. Let me know how those two things work out. Hope this helps,

Andrew

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Anding Member

Anding

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Hi Andrew,

Thank you for these suggestions.  I double checked that Internal Vref is enabled and removed mig.ucf from my project.  I now get the following MAP error.  Please see also an image of the MIG instantiation dialog.  Your further advice would be much appreciated:

ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<2>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<1>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<4>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<3>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<15>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<0>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<9>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<6>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<5>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<8>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<7>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<10>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<11>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<12>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<13>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<14>.
   The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18.
ERROR:Pack:1642 - Errors in physical DRC.

2016-01-29 10_20_43.png

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Anding Member

Anding

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Hello,

I made some further progress since my posting.  I was not aware of it, but the MIG core generator in ISE creates it's own .UCF file in the ipcore_dir/NAME/user_design/constraints folder.  MAP needs to read this file to locate the vref, etc..

However per this answer record sometimes ISE sometimes fails to recognize this UCF file.

http://www.xilinx.com/support/answers/36427.html

The workaround is to copy and rename this file, then manually include it in the project.  I also needed to change the relative paths on two of the INST items by adding "*/" as a prefix

INST "*/u_ddr2_infrastructure/plle2_i" LOC=PLLE2_ADV_X1Y1;
INST "*/u_ddr2_infrastructure/gen_mmcm.mmcm_i" LOC=MMCME2_ADV_X1Y1;

With these adjustments MAP has completed OK.  I have attached my revised UCF file here. 

I wonder if someone familiar with MIG would mind having a quick look and offer feedback on any obvious issues or whether this sounds like the correct approach?

Many thanks,

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Anding Member

Anding

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"File upload failed".  UCF file pasted here

##################################################################################################
##
##  Xilinx, Inc. 2010            www.xilinx.com
##  Tue 26. Jan 16:28:58 2016
##  Generated by MIG Version 1.9
## 
##################################################################################################
##  File name :       MIG7.ucf
##  Details :     Constraints file
##                    FPGA Family:       ARTIX7
##                    FPGA Part:         XC7A100T-CSG324
##                    Speedgrade:        -3
##                    Design Entry:      VHDL
##                    Frequency:         400 MHz
##                    Time Period:       2500 ps
##################################################################################################

##################################################################################################
## Controller 0
## Memory Device: DDR2_SDRAM->Components->MT47H64M16HR-25E
## Data Width: 16
## Time Period: 2500
## Data Mask: 1
##################################################################################################

#NET "sys_clk_i" TNM_NET = TNM_sys_clk;
#TIMESPEC "TS_sys_clk" = PERIOD "TNM_sys_clk" 5 ns;
         
############## NET - IOSTANDARD ##################

NET   "ddr2_dq[0]"                             LOC = "R7"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L23P_T3_34
NET   "ddr2_dq[1]"                             LOC = "V6"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L20N_T3_34
NET   "ddr2_dq[2]"                             LOC = "R8"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L24P_T3_34
NET   "ddr2_dq[3]"                             LOC = "U7"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L22P_T3_34
NET   "ddr2_dq[4]"                             LOC = "V7"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L20P_T3_34
NET   "ddr2_dq[5]"                             LOC = "R6"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L19P_T3_34
NET   "ddr2_dq[6]"                             LOC = "U6"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L22N_T3_34
NET   "ddr2_dq[7]"                             LOC = "R5"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L19N_T3_VREF_34
NET   "ddr2_dq[8]"                             LOC = "T5"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L12P_T1_MRCC_34
NET   "ddr2_dq[9]"                             LOC = "U3"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L8N_T1_34
NET   "ddr2_dq[10]"                            LOC = "V5"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L10P_T1_34
NET   "ddr2_dq[11]"                            LOC = "U4"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L8P_T1_34
NET   "ddr2_dq[12]"                            LOC = "V4"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L10N_T1_34
NET   "ddr2_dq[13]"                            LOC = "T4"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L12N_T1_MRCC_34
NET   "ddr2_dq[14]"                            LOC = "V1"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L7N_T1_34
NET   "ddr2_dq[15]"                            LOC = "T3"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L11N_T1_SRCC_34
NET   "ddr2_addr[12]"                          LOC = "N6"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L18N_T2_34
NET   "ddr2_addr[11]"                          LOC = "K5"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L5P_T0_34
NET   "ddr2_addr[10]"                          LOC = "R2"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L15N_T2_DQS_34
NET   "ddr2_addr[9]"                           LOC = "N5"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L13P_T2_MRCC_34
NET   "ddr2_addr[8]"                           LOC = "L4"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L5N_T0_34
NET   "ddr2_addr[7]"                           LOC = "N1"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L3N_T0_DQS_34
NET   "ddr2_addr[6]"                           LOC = "M2"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L4N_T0_34
NET   "ddr2_addr[5]"                           LOC = "P5"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L13N_T2_MRCC_34
NET   "ddr2_addr[4]"                           LOC = "L3"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L2N_T0_34
NET   "ddr2_addr[3]"                           LOC = "T1"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L17N_T2_34
NET   "ddr2_addr[2]"                           LOC = "M6"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L18P_T2_34
NET   "ddr2_addr[1]"                           LOC = "P4"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L14P_T2_SRCC_34
NET   "ddr2_addr[0]"                           LOC = "M4"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L16P_T2_34
NET   "ddr2_ba[2]"                             LOC = "R1"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L17P_T2_34
NET   "ddr2_ba[1]"                             LOC = "P3"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L14N_T2_SRCC_34
NET   "ddr2_ba[0]"                             LOC = "P2"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L15P_T2_DQS_34
NET   "ddr2_ras_n"                             LOC = "N4"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L16N_T2_34
NET   "ddr2_cas_n"                             LOC = "L1"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L1P_T0_34
NET   "ddr2_we_n"                              LOC = "N2"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L3P_T0_DQS_34
NET   "ddr2_cke[0]"                            LOC = "M1"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L1N_T0_34
NET   "ddr2_odt[0]"                            LOC = "M3"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L4P_T0_34
NET   "ddr2_cs_n[0]"                           LOC = "K6"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_0_34
NET   "ddr2_dm[0]"                             LOC = "T6"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L23N_T3_34
NET   "ddr2_dm[1]"                             LOC = "U1"      |   IOSTANDARD = SSTL18_II            |     SLEW = FAST        ; # Pad function: IO_L7P_T1_34
NET   "ddr2_dqs_p[0]"                          LOC = "U9"      |   IOSTANDARD = DIFF_SSTL18_II       |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L21P_T3_DQS_34
NET   "ddr2_dqs_n[0]"                          LOC = "V9"      |   IOSTANDARD = DIFF_SSTL18_II       |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L21N_T3_DQS_34
NET   "ddr2_dqs_p[1]"                          LOC = "U2"      |   IOSTANDARD = DIFF_SSTL18_II       |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L9P_T1_DQS_34
NET   "ddr2_dqs_n[1]"                          LOC = "V2"      |   IOSTANDARD = DIFF_SSTL18_II       |     SLEW = FAST        |     IN_TERM = UNTUNED_SPLIT_50   ; # Pad function: IO_L9N_T1_DQS_34
NET   "ddr2_ck_p[0]"                           LOC = "L6"      |   IOSTANDARD = DIFF_SSTL18_II       |     SLEW = FAST        ; # Pad function: IO_L6P_T0_34
NET   "ddr2_ck_n[0]"                           LOC = "L5"      |   IOSTANDARD = DIFF_SSTL18_II       |     SLEW = FAST        ; # Pad function: IO_L6N_T0_VREF_34


CONFIG INTERNAL_VREF_BANK34= 0.900;

INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y7;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y5;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y6;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y4;

## INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y7;
## INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y5;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y6;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y4;

 

INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y7;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y5;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y6;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" LOC=OUT_FIFO_X1Y4;

INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y6;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y4;

INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y1;

INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y1;


INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y81;
INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y57;

INST "*/u_ddr2_infrastructure/plle2_i" LOC=PLLE2_ADV_X1Y1;
INST "*/u_ddr2_infrastructure/gen_mmcm.mmcm_i" LOC=MMCME2_ADV_X1Y1;


NET "*/iserdes_clk" TNM_NET = "TNM_ISERDES_CLK";
INST "*/mc0/mc_read_idle_r" TNM = "TNM_SOURCE_IDLE";
INST "*/input_[?].iserdes_dq_.iserdesdq" TNM = "TNM_DEST_ISERDES";
TIMESPEC "TS_ISERDES_CLOCK" = PERIOD "TNM_ISERDES_CLK" 2500 ps;
TIMESPEC TS_MULTICYCLEPATH = FROM "TNM_SOURCE_IDLE" TO "TNM_DEST_ISERDES" TS_ISERDES_CLOCK*6;
     

INST "*/device_temp_sync_r1*" TNM="TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC";
TIMESPEC "TS_MULTICYCLEPATH_DEVICE_TEMP_SYNC" = TO "TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC" 20 ns DATAPATHONLY;

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sLowe Prolific Poster

sLowe

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Hey Anding,

I think this is the correct approach. Off of a couple xilinx support threads a flow similar to this is suggested to get the tools to see that .ucf file. http://www.xilinx.com/support/answers/37424.html Seems like this stems from creating the ip from the project manager instead of a standalone core generator.

The link you found is much easier to follow and should be used. For future readers that link is copied from an earlier post below.

http://www.xilinx.com/support/answers/36427.html

I will also put in a note on the ram2ddr component wiki page.

Thanks for the info!

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