I'm sure that someone has used a PLL in an Arty design....I have tried and keep getting an implementation error as follows:
[DRC 23-20] Rule violation (REQP-1712) Input clock driver - Unsupported PLLE2_ADV connectivity. The signal xilinx_ip_pll/inst/clk_in1 on the xilinx_ip_pll/inst/plle2_adv_inst/CLKIN1 pin of xilinx_ip_pll/inst/plle2_adv_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO.
The Arty Clock100 comes in on Pin E3, so I'm assuming that this is a clock capable input..? (can't be moved...) I even tried instantiating a BUFH in the top level before the PLL input and no dice...
New to Vivado so I'm sure that this is another basic cockpit error...
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ASICs
Hi everyone,
I'm sure that someone has used a PLL in an Arty design....I have tried and keep getting an implementation error as follows:
[DRC 23-20] Rule violation (REQP-1712) Input clock driver - Unsupported PLLE2_ADV connectivity. The signal xilinx_ip_pll/inst/clk_in1 on the xilinx_ip_pll/inst/plle2_adv_inst/CLKIN1 pin of xilinx_ip_pll/inst/plle2_adv_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO.
The Arty Clock100 comes in on Pin E3, so I'm assuming that this is a clock capable input..? (can't be moved...) I even tried instantiating a BUFH in the top level before the PLL input and no dice...
New to Vivado so I'm sure that this is another basic cockpit error...
Thanks in advance.
Paul
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