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ASICs

Simple Counter to drive LEDs Arty Board

Question

Hello All, 

Just joined the forum, I just received my Arty board, and ported a very simple 32 bit counter design that drives LEDs (slower bits). I can synthesize and implement the design (no warnings), I can view the schematic and it looks exactly like the RTL, however, when I try to load it onto the target I get the following warning:

WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3.
Resolution: 
1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR
2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub].

The board does nothing! I use this exact same code on another FPGA board (Altera Cyclone-5) and it works fine...

I'm assuming that the above warning is critical because after the download the boards doesn't do anything

Thanks for any help!

-Paul 

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As far as I can tell, that warning is always there unless you include some of the debug IP in your design. When I get issues like you have, it is normally because I've forgot to assign the clock). Can double-check the contents of your XDC file?

The other problem i've had on other boards is that I've generated the bitstream for the wrong FPGA device (e.g. incorrect package) - but Vivado should pick that up for you.

If you like, post the source files here we should be able to fix it pretty quickly.

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Hi Paul,

It is difficult to pinpoint your problem without knowing where the project was ported from. Is your code purely HDL? Which version of Vivado are you using? It looks like you are trying to connect a debugger, do you know what this might be?

Thanks,

Tommy

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Thank you for your input....It was in fact just a warning due to "no debug logic", I found that the "reset" to the PLL was not connected properly so the rest of the logic had no clock from the PLL.... I'm new to Vivado so I assumed I was doing something really bad (other than a wiring cockpit error!).... Thanks Again! 

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