Slow synthesis and implementation

[Alex]

A professor is going to switch from Spartan 3 to Nexys 4 DDR. He comes up the following problem.

We’re still experiencing significantly longer synthesis/implementation times in ISE for Artix-7, compared to Spartan 3. I also tried the designs in Vivado, with similar results.  This does depend a lot on the CPU in the computer running the software. My laptop (Intel Core i7)  took 3:45 to do synthesis through place and route, whereas it took 9:26 in the lab and my desktop PC (Intel Core2 Quad Q8400). Add additional time for generating a configuration file.  The Nexys4 sample project took over 13 minutes for implementation on my office PC.

 

If there are any project options that you know of that would shorten this time, we would love to try them out.

I have tried changing “Flow_RuntimeOptimize” to “Flow_Quick”, but for simple designs this only cut off a couple of seconds.

 

[Commanderfranz]

Hi Alex,

I'm am not at all suprised that the Nexys 4 DDR takes longer in implementation and bitstream than does the Spartan 3. The Nexys 4 has an Artix 7 FPGA rather than the Spartan 3 FPGA. The Artix 7 is a much larger and more complex FPGA so that software has more configuring to do than on the Spartan 3.  

As far as the specific times he gave, for a fairly complex design around 4 minutes on an i7 is not at all surprising. If he tells me which sample project I can tell specifically if this is expected.

As far as settings go to shorten the build time, I would recognize posting on the Xilinx forums as they are the ones that make the software.

Hope this helps!

Kaitlyn 

[Alex]

Hi Kaitlyn, OK. I will let the professor know and see if he can give us the sample project. I can try to see how complex it is.