Errors in such a simple design flow are very surprising. Anyone have a clue as to how to fix this? Why is a design that cannot build being offered as the base for Arty?
Following the instructions exactly gives the following results:
[Common 17-55] 'get_property' expects at least one object.
[Common 17-55] 'get_property' expects at least one object.
[Common 17-55] 'get_property' expects at least one object.
[Common 17-55] 'get_property' expects at least one object.
[IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2015.2/data/ip/xilinx/axi_gpio_v2_0/utils/board/board.xit': ERROR: [Common 17-55] 'get_property' expects at least one object. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
[IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2015.2/data/ip/xilinx/axi_gpio_v2_0/utils/board/board.xit': ERROR: [Common 17-55] 'get_property' expects at least one object. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
[IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2015.2/data/ip/xilinx/axi_gpio_v2_0/utils/board/board.xit': ERROR: [Common 17-55] 'get_property' expects at least one object. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
[IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2015.2/data/ip/xilinx/axi_gpio_v2_0/utils/board/board.xit': ERROR: [Common 17-55] 'get_property' expects at least one object. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
[IP_Flow 19-167] Failed to deliver one or more file(s).
[IP_Flow 19-167] Failed to deliver one or more file(s).
[IP_Flow 19-167] Failed to deliver one or more file(s).
[IP_Flow 19-167] Failed to deliver one or more file(s).
[IP_Flow 19-911] XIT detected an open writer channel for file 'f:/D/arty_bsd/arty_bsd.srcs/sources_1/bd/system/ip/system_axi_gpio_0_0/system_axi_gpio_0_0_board.xdc'. Please use 'close_ipfile' command to close channels before exit.
[IP_Flow 19-911] XIT detected an open writer channel for file 'f:/D/arty_bsd/arty_bsd.srcs/sources_1/bd/system/ip/system_axi_gpio_1_0/system_axi_gpio_1_0_board.xdc'. Please use 'close_ipfile' command to close channels before exit.
[IP_Flow 19-911] XIT detected an open writer channel for file 'f:/D/arty_bsd/arty_bsd.srcs/sources_1/bd/system/ip/system_axi_gpio_0_0/system_axi_gpio_0_0_board.xdc'. Please use 'close_ipfile' command to close channels before exit.
[IP_Flow 19-911] XIT detected an open writer channel for file 'f:/D/arty_bsd/arty_bsd.srcs/sources_1/bd/system/ip/system_axi_gpio_1_0/system_axi_gpio_1_0_board.xdc'. Please use 'close_ipfile' command to close channels before exit.
[IP_Flow 19-3505] IP Generation error: Failed to generate IP 'system_axi_gpio_0_0'. Failed to generate 'Implementation' outputs:
[IP_Flow 19-3505] IP Generation error: Failed to generate IP 'system_axi_gpio_1_0'. Failed to generate 'Implementation' outputs:
[IP_Flow 19-3505] IP Generation error: Failed to generate IP 'system_axi_gpio_0_0'. Failed to generate 'Implementation' outputs:
[IP_Flow 19-3505] IP Generation error: Failed to generate IP 'system_axi_gpio_1_0'. Failed to generate 'Implementation' outputs:
[IP_Flow 19-98] Generation of the IP CORE failed. Failed to generate IP 'system_axi_gpio_0_0'. Failed to generate 'Implementation' outputs:
[IP_Flow 19-98] Generation of the IP CORE failed. Failed to generate IP 'system_axi_gpio_1_0'. Failed to generate 'Implementation' outputs:
[IP_Flow 19-98] Generation of the IP CORE failed. Failed to generate IP 'system_axi_gpio_0_0'. Failed to generate 'Implementation' outputs:
[IP_Flow 19-98] Generation of the IP CORE failed. Failed to generate IP 'system_axi_gpio_1_0'. Failed to generate 'Implementation' outputs:
[BD 41-1030] Generation failed for the IP Integrator block axi_gpio_0
[BD 41-1030] Generation failed for the IP Integrator block axi_gpio_1
[BD 41-1030] Generation failed for the IP Integrator block axi_gpio_0
[BD 41-1030] Generation failed for the IP Integrator block axi_gpio_1
Implementation Place Design [Place 30-58] IO placement is infeasible. Number of unplaced terminals (36) is greater than number of available sites (0). The following Groups of I/O terminals have not sufficient capacity: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: BiDi RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 36 sites. Term: shield_dp0_dp19_tri_io[0] Term: shield_dp0_dp19_tri_io[1] Term: shield_dp0_dp19_tri_io[2] Term: shield_dp0_dp19_tri_io[3] Term: shield_dp0_dp19_tri_io[4] Term: shield_dp0_dp19_tri_io[5] Term: shield_dp0_dp19_tri_io[6] Term: shield_dp0_dp19_tri_io[7] Term: shield_dp0_dp19_tri_io[8] Term: shield_dp0_dp19_tri_io[9] Term: shield_dp0_dp19_tri_io[10] Term: shield_dp0_dp19_tri_io[11] Term: shield_dp0_dp19_tri_io[12] Term: shield_dp0_dp19_tri_io[13] Term: shield_dp0_dp19_tri_io[14] Term: shield_dp0_dp19_tri_io[15] Term: shield_dp0_dp19_tri_io[16] Term: shield_dp0_dp19_tri_io[17] Term: shield_dp0_dp19_tri_io[18] Term: shield_dp0_dp19_tri_io[19] Term: shield_dp26_dp41_tri_io[0] Term: shield_dp26_dp41_tri_io[1] Term: shield_dp26_dp41_tri_io[2] Term: shield_dp26_dp41_tri_io[3] Term: shield_dp26_dp41_tri_io[4] Term: shield_dp26_dp41_tri_io[5] Term: shield_dp26_dp41_tri_io[6] Term: shield_dp26_dp41_tri_io[7] Term: shield_dp26_dp41_tri_io[8] Term: shield_dp26_dp41_tri_io[9] Term: shield_dp26_dp41_tri_io[10] Term: shield_dp26_dp41_tri_io[11] Term: shield_dp26_dp41_tri_io[12] Term: shield_dp26_dp41_tri_io[13] Term: shield_dp26_dp41_tri_io[14] Term: and shield_dp26_dp41_tri_io[15]
[Place 30-374] IO placer failed to find a solution Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.
[Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances
Question
nickh
Build errors are in the documentation / design located at:
https://reference.digilentinc.com/arty:basedesign
Errors in such a simple design flow are very surprising. Anyone have a clue as to how to fix this? Why is a design that cannot build being offered as the base for Arty?
Following the instructions exactly gives the following results:
++++++++++++++++++++++++++++++Run Logs++++++++++++++++++++++++++
Vivado Commands
launch_runs impl_1 -to_step write_bitstream -jobs 8
[Common 17-55] 'get_property' expects at least one object.
[Common 17-55] 'get_property' expects at least one object.
[Common 17-55] 'get_property' expects at least one object.
[Common 17-55] 'get_property' expects at least one object.
[IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2015.2/data/ip/xilinx/axi_gpio_v2_0/utils/board/board.xit': ERROR: [Common 17-55] 'get_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
[IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2015.2/data/ip/xilinx/axi_gpio_v2_0/utils/board/board.xit': ERROR: [Common 17-55] 'get_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
[IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2015.2/data/ip/xilinx/axi_gpio_v2_0/utils/board/board.xit': ERROR: [Common 17-55] 'get_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
[IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2015.2/data/ip/xilinx/axi_gpio_v2_0/utils/board/board.xit': ERROR: [Common 17-55] 'get_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
[IP_Flow 19-167] Failed to deliver one or more file(s).
[IP_Flow 19-167] Failed to deliver one or more file(s).
[IP_Flow 19-167] Failed to deliver one or more file(s).
[IP_Flow 19-167] Failed to deliver one or more file(s).
[IP_Flow 19-911] XIT detected an open writer channel for file 'f:/D/arty_bsd/arty_bsd.srcs/sources_1/bd/system/ip/system_axi_gpio_0_0/system_axi_gpio_0_0_board.xdc'. Please use 'close_ipfile' command to close channels before exit.
[IP_Flow 19-911] XIT detected an open writer channel for file 'f:/D/arty_bsd/arty_bsd.srcs/sources_1/bd/system/ip/system_axi_gpio_1_0/system_axi_gpio_1_0_board.xdc'. Please use 'close_ipfile' command to close channels before exit.
[IP_Flow 19-911] XIT detected an open writer channel for file 'f:/D/arty_bsd/arty_bsd.srcs/sources_1/bd/system/ip/system_axi_gpio_0_0/system_axi_gpio_0_0_board.xdc'. Please use 'close_ipfile' command to close channels before exit.
[IP_Flow 19-911] XIT detected an open writer channel for file 'f:/D/arty_bsd/arty_bsd.srcs/sources_1/bd/system/ip/system_axi_gpio_1_0/system_axi_gpio_1_0_board.xdc'. Please use 'close_ipfile' command to close channels before exit.
[IP_Flow 19-3505] IP Generation error: Failed to generate IP 'system_axi_gpio_0_0'. Failed to generate 'Implementation' outputs:
[IP_Flow 19-3505] IP Generation error: Failed to generate IP 'system_axi_gpio_1_0'. Failed to generate 'Implementation' outputs:
[IP_Flow 19-3505] IP Generation error: Failed to generate IP 'system_axi_gpio_0_0'. Failed to generate 'Implementation' outputs:
[IP_Flow 19-3505] IP Generation error: Failed to generate IP 'system_axi_gpio_1_0'. Failed to generate 'Implementation' outputs:
[IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'system_axi_gpio_0_0'. Failed to generate 'Implementation' outputs:
[IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'system_axi_gpio_1_0'. Failed to generate 'Implementation' outputs:
[IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'system_axi_gpio_0_0'. Failed to generate 'Implementation' outputs:
[IP_Flow 19-98] Generation of the IP CORE failed.
Failed to generate IP 'system_axi_gpio_1_0'. Failed to generate 'Implementation' outputs:
[BD 41-1030] Generation failed for the IP Integrator block axi_gpio_0
[BD 41-1030] Generation failed for the IP Integrator block axi_gpio_1
[BD 41-1030] Generation failed for the IP Integrator block axi_gpio_0
[BD 41-1030] Generation failed for the IP Integrator block axi_gpio_1
Implementation
Place Design
[Place 30-58] IO placement is infeasible. Number of unplaced terminals (36) is greater than number of available sites (0).
The following Groups of I/O terminals have not sufficient capacity:
IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: BiDi RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 36 sites.
Term: shield_dp0_dp19_tri_io[0]
Term: shield_dp0_dp19_tri_io[1]
Term: shield_dp0_dp19_tri_io[2]
Term: shield_dp0_dp19_tri_io[3]
Term: shield_dp0_dp19_tri_io[4]
Term: shield_dp0_dp19_tri_io[5]
Term: shield_dp0_dp19_tri_io[6]
Term: shield_dp0_dp19_tri_io[7]
Term: shield_dp0_dp19_tri_io[8]
Term: shield_dp0_dp19_tri_io[9]
Term: shield_dp0_dp19_tri_io[10]
Term: shield_dp0_dp19_tri_io[11]
Term: shield_dp0_dp19_tri_io[12]
Term: shield_dp0_dp19_tri_io[13]
Term: shield_dp0_dp19_tri_io[14]
Term: shield_dp0_dp19_tri_io[15]
Term: shield_dp0_dp19_tri_io[16]
Term: shield_dp0_dp19_tri_io[17]
Term: shield_dp0_dp19_tri_io[18]
Term: shield_dp0_dp19_tri_io[19]
Term: shield_dp26_dp41_tri_io[0]
Term: shield_dp26_dp41_tri_io[1]
Term: shield_dp26_dp41_tri_io[2]
Term: shield_dp26_dp41_tri_io[3]
Term: shield_dp26_dp41_tri_io[4]
Term: shield_dp26_dp41_tri_io[5]
Term: shield_dp26_dp41_tri_io[6]
Term: shield_dp26_dp41_tri_io[7]
Term: shield_dp26_dp41_tri_io[8]
Term: shield_dp26_dp41_tri_io[9]
Term: shield_dp26_dp41_tri_io[10]
Term: shield_dp26_dp41_tri_io[11]
Term: shield_dp26_dp41_tri_io[12]
Term: shield_dp26_dp41_tri_io[13]
Term: shield_dp26_dp41_tri_io[14]
Term: and shield_dp26_dp41_tri_io[15]
[Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| IO Placement : Bank Stats |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| Id | Pins | Terms | Standards | IDelayCtrls | VREF | VCCO | VR | DCI |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| 0 | 0 | 0 | | | | | | |
| 14 | 50 | 9 | LVCMOS33(9) | | | +3.30 | YES | |
| 15 | 50 | 31 | LVCMOS33(31) | | | +3.30 | YES | |
| 16 | 10 | 10 | LVCMOS33(10) | | | +3.30 | YES | |
| 34 | 50 | 48 | SSTL135(42) DIFF_SSTL135(6) | | +0.68 | +1.35 | YES | |
| 35 | 50 | 36 | LVCMOS33(36) | | | +3.30 | YES | |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| | 210 | 134 | | | | | | |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
IO Placement:
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| BankId | Terminal | Standard | Site | Pin | Attributes |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 14 | i2c_scl_io | LVCMOS33 | IOB_X0Y42 | L18 | |
| | i2c_sda_io | LVCMOS33 | IOB_X0Y41 | M18 | |
| | led_4bits_tri_o[2] | LVCMOS33 | IOB_X0Y2 | T9 | |
| | led_4bits_tri_o[3] | LVCMOS33 | IOB_X0Y1 | T10 | |
| | qspi_flash_io0_io | LVCMOS33 | IOB_X0Y48 | K17 | |
| | qspi_flash_io1_io | LVCMOS33 | IOB_X0Y47 | K18 | |
| | qspi_flash_io2_io | LVCMOS33 | IOB_X0Y46 | L14 | |
| | qspi_flash_io3_io | LVCMOS33 | IOB_X0Y45 | M14 | |
| | qspi_flash_ss_io | LVCMOS33 | IOB_X0Y38 | L13 | |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 15 | Vaux0_v_n | LVCMOS33 | IOB_X0Y97 | C14 | |
| | Vaux0_v_p | LVCMOS33 | IOB_X0Y98 | D14 | |
| | Vaux10_v_n | LVCMOS33 | IOB_X0Y83 | A16 | |
| | Vaux10_v_p | LVCMOS33 | IOB_X0Y84 | A15 | |
| | Vaux1_v_n | LVCMOS33 | IOB_X0Y93 | B12 | |
| | Vaux1_v_p | LVCMOS33 | IOB_X0Y94 | C12 | |
| | Vaux2_v_n | LVCMOS33 | IOB_X0Y85 | B17 | |
| | Vaux2_v_p | LVCMOS33 | IOB_X0Y86 | B16 | |
| | Vaux9_v_n | LVCMOS33 | IOB_X0Y89 | F14 | |
| | Vaux9_v_p | LVCMOS33 | IOB_X0Y90 | F13 | |
| | eth_mdio_mdc_mdc | LVCMOS33 | IOB_X0Y71 | F16 | |
| | eth_mdio_mdc_mdio_io | LVCMOS33 | IOB_X0Y66 | K13 | |
| | eth_mii_col | LVCMOS33 | IOB_X0Y67 | D17 | |
| | eth_mii_crs | LVCMOS33 | IOB_X0Y69 | G14 | |
| | eth_mii_rst_n | LVCMOS33 | IOB_X0Y60 | C16 | |
| | eth_mii_rx_clk | LVCMOS33 | IOB_X0Y72 | F15 | |
| | eth_mii_rx_dv | LVCMOS33 | IOB_X0Y73 | G16 | |
| | eth_mii_rx_er | LVCMOS33 | IOB_X0Y59 | C17 | |
| | eth_mii_rxd[0] | LVCMOS33 | IOB_X0Y57 | D18 | |
| | eth_mii_rxd[1] | LVCMOS33 | IOB_X0Y68 | E17 | |
| | eth_mii_rxd[2] | LVCMOS33 | IOB_X0Y58 | E18 | |
| | eth_mii_rxd[3] | LVCMOS33 | IOB_X0Y63 | G17 | |
| | eth_mii_tx_clk | LVCMOS33 | IOB_X0Y74 | H16 | |
| | eth_mii_tx_en | LVCMOS33 | IOB_X0Y61 | H15 | * |
| | eth_mii_txd[0] | LVCMOS33 | IOB_X0Y70 | H14 | |
| | eth_mii_txd[1] | LVCMOS33 | IOB_X0Y62 | J14 | |
| | eth_mii_txd[2] | LVCMOS33 | IOB_X0Y65 | J13 | |
| | eth_mii_txd[3] | LVCMOS33 | IOB_X0Y64 | H17 | |
| | eth_ref_clk | LVCMOS33 | IOB_X0Y56 | G18 | |
| | i2c_pullups_tri_o[0] | LVCMOS33 | IOB_X0Y81 | A14 | |
| | i2c_pullups_tri_o[1] | LVCMOS33 | IOB_X0Y82 | A13 | |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 16 | tches_4bits_tri_i[0] | LVCMOS33 | IOB_X0Y125 | A8 | |
| | tches_4bits_tri_i[1] | LVCMOS33 | IOB_X0Y124 | C11 | |
| | tches_4bits_tri_i[2] | LVCMOS33 | IOB_X0Y123 | C10 | |
| | tches_4bits_tri_i[3] | LVCMOS33 | IOB_X0Y122 | A10 | |
| | ttons_4bits_tri_i[0] | LVCMOS33 | IOB_X0Y137 | D9 | * |
| | ttons_4bits_tri_i[1] | LVCMOS33 | IOB_X0Y128 | C9 | |
| | ttons_4bits_tri_i[2] | LVCMOS33 | IOB_X0Y127 | B9 | |
| | ttons_4bits_tri_i[3] | LVCMOS33 | IOB_X0Y126 | B8 | |
| | usb_uart_rxd | LVCMOS33 | IOB_X0Y121 | A9 | |
| | usb_uart_txd | LVCMOS33 | IOB_X0Y111 | D10 | * |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 34 | DDR3_ck_p[0] | DIFF_SSTL135 | IOB_X1Y8 | U9 | |
| | DDR3_ck_n[0] | DIFF_SSTL135 | IOB_X1Y7 | V9 | |
| | DDR3_dqs_p[0] | DIFF_SSTL135 | IOB_X1Y44 | N2 | |
| | DDR3_dqs_n[0] | DIFF_SSTL135 | IOB_X1Y43 | N1 | |
| | DDR3_dqs_p[1] | DIFF_SSTL135 | IOB_X1Y32 | U2 | |
| | DDR3_dqs_n[1] | DIFF_SSTL135 | IOB_X1Y31 | V2 | |
| | DDR3_addr[0] | SSTL135 | IOB_X1Y19 | R2 | VRef=+0.68 |
| | DDR3_addr[10] | SSTL135 | IOB_X1Y12 | R6 | VRef=+0.68 |
| | DDR3_addr[11] | SSTL135 | IOB_X1Y5 | U6 | VRef=+0.68 |
| | DDR3_addr[12] | SSTL135 | IOB_X1Y3 | T6 | VRef=+0.68 |
| | DDR3_addr[13] | SSTL135 | IOB_X1Y1 | T8 | VRef=+0.68 |
| | DDR3_addr[1] | SSTL135 | IOB_X1Y14 | M6 | VRef=+0.68 |
| | DDR3_addr[2] | SSTL135 | IOB_X1Y17 | N4 | VRef=+0.68 |
| | DDR3_addr[3] | SSTL135 | IOB_X1Y15 | T1 | VRef=+0.68 |
| | DDR3_addr[4] | SSTL135 | IOB_X1Y13 | N6 | VRef=+0.68 |
| | DDR3_addr[5] | SSTL135 | IOB_X1Y4 | R7 | VRef=+0.68 |
| | DDR3_addr[6] | SSTL135 | IOB_X1Y9 | V6 | VRef=+0.68 |
| | DDR3_addr[7] | SSTL135 | IOB_X1Y6 | U7 | VRef=+0.68 |
| | DDR3_addr[8] | SSTL135 | IOB_X1Y2 | R8 | VRef=+0.68 |
| | DDR3_addr[9] | SSTL135 | IOB_X1Y10 | V7 | VRef=+0.68 |
| | DDR3_ba[0] | SSTL135 | IOB_X1Y16 | R1 | VRef=+0.68 |
| | DDR3_ba[1] | SSTL135 | IOB_X1Y22 | P4 | VRef=+0.68 |
| | DDR3_ba[2] | SSTL135 | IOB_X1Y20 | P2 | VRef=+0.68 |
| | DDR3_cas_n | SSTL135 | IOB_X1Y18 | M4 | VRef=+0.68 |
| | DDR3_cke[0] | SSTL135 | IOB_X1Y24 | N5 | VRef=+0.68 |
| | DDR3_cs_n[0] | SSTL135 | IOB_X1Y0 | U8 | VRef=+0.68 |
| | DDR3_dm[0] | SSTL135 | IOB_X1Y48 | L1 | VRef=+0.68 |
| | DDR3_dm[1] | SSTL135 | IOB_X1Y36 | U1 | VRef=+0.68 |
| | DDR3_dq[0] | SSTL135 | IOB_X1Y40 | K5 | VRef=+0.68 |
| | DDR3_dq[10] | SSTL135 | IOB_X1Y34 | U4 | VRef=+0.68 |
| | DDR3_dq[11] | SSTL135 | IOB_X1Y30 | V5 | VRef=+0.68 |
| | DDR3_dq[12] | SSTL135 | IOB_X1Y35 | V1 | VRef=+0.68 |
| | DDR3_dq[13] | SSTL135 | IOB_X1Y27 | T3 | VRef=+0.68 |
| | DDR3_dq[14] | SSTL135 | IOB_X1Y33 | U3 | VRef=+0.68 |
| | DDR3_dq[15] | SSTL135 | IOB_X1Y28 | R3 | VRef=+0.68 |
| | DDR3_dq[1] | SSTL135 | IOB_X1Y45 | L3 | VRef=+0.68 |
| | DDR3_dq[2] | SSTL135 | IOB_X1Y46 | K3 | VRef=+0.68 |
| | DDR3_dq[3] | SSTL135 | IOB_X1Y38 | L6 | VRef=+0.68 |
| | DDR3_dq[4] | SSTL135 | IOB_X1Y42 | M3 | VRef=+0.68 |
| | DDR3_dq[5] | SSTL135 | IOB_X1Y47 | M1 | VRef=+0.68 |
| | DDR3_dq[6] | SSTL135 | IOB_X1Y39 | L4 | VRef=+0.68 |
| | DDR3_dq[7] | SSTL135 | IOB_X1Y41 | M2 | VRef=+0.68 |
| | DDR3_dq[8] | SSTL135 | IOB_X1Y29 | V4 | VRef=+0.68 |
| | DDR3_dq[9] | SSTL135 | IOB_X1Y26 | T5 | VRef=+0.68 |
| | DDR3_odt[0] | SSTL135 | IOB_X1Y11 | R5 | VRef=+0.68* |
| | DDR3_ras_n | SSTL135 | IOB_X1Y21 | P3 | VRef=+0.68 |
| | DDR3_reset_n | SSTL135 | IOB_X1Y49 | K6 | VRef=+0.68 |
| | DDR3_we_n | SSTL135 | IOB_X1Y23 | P5 | VRef=+0.68 |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 35 | Vaux12_v_n | LVCMOS33 | IOB_X1Y95 | B6 | |
| | Vaux12_v_p | LVCMOS33 | IOB_X1Y96 | B7 | |
| | Vaux13_v_n | LVCMOS33 | IOB_X1Y89 | E5 | |
| | Vaux13_v_p | LVCMOS33 | IOB_X1Y90 | E6 | |
| | Vaux14_v_n | LVCMOS33 | IOB_X1Y83 | A3 | |
| | Vaux14_v_p | LVCMOS33 | IOB_X1Y84 | A4 | |
| | Vaux15_v_n | LVCMOS33 | IOB_X1Y79 | B2 | |
| | Vaux15_v_p | LVCMOS33 | IOB_X1Y80 | B3 | |
| | Vaux4_v_n | LVCMOS33 | IOB_X1Y97 | C5 | |
| | Vaux4_v_p | LVCMOS33 | IOB_X1Y98 | C6 | |
| | Vaux5_v_n | LVCMOS33 | IOB_X1Y93 | A5 | |
| | Vaux5_v_p | LVCMOS33 | IOB_X1Y94 | A6 | |
| | Vaux6_v_n | LVCMOS33 | IOB_X1Y85 | B4 | |
| | Vaux6_v_p | LVCMOS33 | IOB_X1Y86 | C4 | |
| | Vaux7_v_n | LVCMOS33 | IOB_X1Y81 | A1 | |
| | Vaux7_v_p | LVCMOS33 | IOB_X1Y82 | B1 | |
| | led_4bits_tri_o[0] | LVCMOS33 | IOB_X1Y51 | H5 | |
| | led_4bits_tri_o[1] | LVCMOS33 | IOB_X1Y50 | J5 | |
| | reset | LVCMOS33 | IOB_X1Y68 | C2 | |
| | rgb_led_tri_o[0] | LVCMOS33 | IOB_X1Y63 | E1 | |
| | rgb_led_tri_o[10] | LVCMOS33 | IOB_X1Y52 | H6 | |
| | rgb_led_tri_o[11] | LVCMOS33 | IOB_X1Y53 | K1 | |
| | rgb_led_tri_o[1] | LVCMOS33 | IOB_X1Y61 | F6 | * |
| | rgb_led_tri_o[2] | LVCMOS33 | IOB_X1Y62 | G6 | |
| | rgb_led_tri_o[3] | LVCMOS33 | IOB_X1Y60 | G4 | |
| | rgb_led_tri_o[4] | LVCMOS33 | IOB_X1Y58 | J4 | |
| | rgb_led_tri_o[5] | LVCMOS33 | IOB_X1Y59 | G3 | |
| | rgb_led_tri_o[6] | LVCMOS33 | IOB_X1Y57 | H4 | |
| | rgb_led_tri_o[7] | LVCMOS33 | IOB_X1Y55 | J2 | |
| | rgb_led_tri_o[8] | LVCMOS33 | IOB_X1Y56 | J3 | |
| | rgb_led_tri_o[9] | LVCMOS33 | IOB_X1Y54 | K2 | |
| | spi_io0_io | LVCMOS33 | IOB_X1Y65 | G1 | |
| | spi_io1_io | LVCMOS33 | IOB_X1Y66 | H1 | |
| | spi_sck_io | LVCMOS33 | IOB_X1Y64 | F1 | |
| | spi_ss_io | LVCMOS33 | IOB_X1Y67 | C1 | |
| | sys_clock | LVCMOS33 | IOB_X1Y76 | E3 | |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances
++++++++++++++++++++++++++++End Log++++++++++++++++++++++++
Thanks
Nick
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