Multiplier - bus size change

[Antek]

Hello,

I use ISE Xilinx 14.7. I have got some problem with using ready multipliers.

These multiplier have 18bit inputs and 36 bit output but I need to use different size of a signal.  I could add/substract some leading zeros but I am not sure how to do it in schematic.

Arrows on the picture shows places of my problem.

 

Is there any easy way to change size of a vector in schematic?

[sLowe]

Hey Antek,

A quick solution that comes to mind would be to make your own bus truncate with HDL and then generate the schematic symbol for it. You would then place your block in between your multiplier and your adder

http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/pp_p_process_create_schematic_symbol.htm

in is 35 bit logic vector and out is 16 bit logic vector

out(15 downto 0) <= in(15 downto 0); 

You could also put in an overflow indicator in case your multiply goes above 65k.

- Sam