NexysVideo PHY-MAC routed delay path

[s71239@]

In data sheet for Realtek 8211E-VG on page 65  for TskewRX is wroten

"This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5ns and less thsn 2.0ns will be added to the associated clock signal"

Where i can get information about routed path for RX-DATA and RXCLK on the digilinet Nexys Video board.

There is a table for delay time for all routed path for this board?

I need delay time regarding RXCLK  2ns. But if board give via routed path additional 2ns , then is too much for my design.

Please help!!!!

[s71239@]

It's look like , that the delay path on the board is routed as shown. See picture.

But i need if it is possible, a exact value of delay time for they paths.

Thanks

s71239

[Tickstart]

17 hours ago, s71239@ said:

is wroten

:'D reminds me of: https://youtu.be/vH2-sXTmzWI?t=20m13s

 

[Jens]

Hello,

since one can see only a small amount of the routed wires on the PCB top and bottom layer the only confident source of the delay values is the PCB layout.

In this case, the absolute delays are not of interest but the difference in delays between the data lines and clocks (rx and tx).

The delay of the rx-clk-line may also be influenced by C23 (22pF to GND).

Jens

[jpeyron]

Hi @s71239@,

I have reached out to one of our layout engineers about this forum thread. It maybe a few days before i get a response.

thank you,

Jon

[Jens]

Hello Jon,

could the layout engineer already have a look at this topic?

Thanks a lot!

Jens

[jpeyron]

Hi @Jens,

I have reached out to them again about your thread.  I am sorry about the delay due to the holiday/vacation. We should hear back from them in the next couple days.

thank you,

Jon

[elodg]

The skew demanded by the RGMII specs between clock and data groups has not been implemented on the PCB. See the trace lengths below (unit mm) for delay matching inside the signal groups.

This implies that the skew must be implemented in the MAC and/or PHY. The PHY has internal delays that are configurable by pull resistors on pins 32 and 16: R88/83 and R72/79. The board is shipping with no PHY delays enabled as written in the reference manual:

Quote

  * No delay for TXD and RXD relative to TXC and RXC for data latching (RXDLY, TXDLY)

You may change these on your board.

The reason for no delay matching by default is because of the flexibility in MAC implementation in the FPGA. Check the exact MAC IP for delay matching. If it is not readily configurable, enable it in the PHY instead.

[Jens]

Hello @elodg,

many thanks for the information! The length (in picoseconds?) is equal for all rx wires and for all rx wires.

For me it remains unclear if C23 (22pF to GND) adds an delay to eth_rxck or not.

Many thanks in advance!

Jens

[elodg]

It was left off from the capture, but those values are trace lengths in mm. C23 is reserved there for EMC purposes, it has nothing to do with the delays you are looking for.

[Jens]

Thank you very much indeed!

Jens

[s71239@]

Hi Jon, elodg,

thank you very much for your research.

This topic is closed.

Damir