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Digital Discovery - some questions.


Piotr Rzeszut

Question

Hi.

I am getting my DD soon and I have been exploring some options using live demo of WaveForms 3.8.2. I have following questions:

1. How can I implement state machines using ROM logic (for example Moore State Machine), as stated in specs (https://reference.digilentinc.com/reference/instrumentation/digital-discovery/specifications):

Quote

ROM logic for implementing user-defined Boolean functions and State Machines

2. Why I am not able to select DIO39 ar ROM Logic input, while I am able to select it as ROM Logic output?

image.png.6b65f22a4166c1109628fd86d5802a36.pngimage.png.6457e6df3505d50a34f5f9e33fa83fe7.png

3. Well, It would be also nice to allow using DIN0..23 as ROM Logic inputs

4. Is there a possibility to config inputs as LVDS/differential? Ex. DIN0 and DIN1 as an LVDS input channel?

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Hi @Piotr Rzeszut

Sorry for the late reply but I was busy with some urgent project...

1. You can define the state machine using the Patterns/ROM Logic/Truth table
https://reference.digilentinc.com/learn/instrumentation/tutorials/ad2-pattern-generator/start
https://reference.digilentinc.com/waveforms_-_rom_logic

2. The inputs for the ROM logic are used to address the buffer, so having 32k (2^15) buffer you have 15 inputs, DIO 0-14 aka DIO 24-39 on Digital Discovery 

3. The input line are hardcoded. It would be complicated to implement and even more complicated to use configurable input order...

4. No LVDS. Such would require dedicated connector, line termination... basically a different device for each protocol...

5. Please use the manual in the SDK installed by WaveForms:
C:\Program Files (x86)\Digilent\WaveFormsSDK\ WaveForms SDK Reference Manual.pdf

12.4 Digital Discovery
For the DigitalOut and IO functions, and AnalogIO DIOPP/PE the indexing 15:0 refers to DIO39:24.
...

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Hi @attila,

The support is one of the fastest I experienced, so there is no reason to say sorry ;)

1. Thank you for the second link - it explained everything I wanted to know.

2. So the input number is limited to 15 lines.

3. Right, this would require changing FPGA configuration

4. Yes, the best option would be to design own probe adapter with dedicated transceivers

5. Thank you for pointing out the paragraph - I noticed only information about AnalogIO DIOPP/PE

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