ZYNQ -7020 Development Board OOB code

[ArKay99]

I just purchased a ZYNQ-7020 Development board for my development and learning purposes. Just out of the box, it's pretty amazing and I'm anxious to dive in and start kicking the tires...so here's my question and resulting dilemma. I found what appears to be the code at the bottom of the product page. I downloaded and installed it and upon reading the readme discovered that it will only work with Vivado 2016.4. So, I downloaded and installed 2016.4 from the archives, after I discovered that Vivado can have multiple versions coexist on the same machine (thank you Xilinx).

After the install I launched Vivado 2016.4 and took the actions stated in the readme and invoked the create_project.tcl script. It ran for a while and near the end it failed with a few critical errors stating there were a few components that could not be found. I did install the ip and if folders in the vivado-library folder in the common-repo folder (they were in the local folder adjacent to the vivado-library folder which was empty). Upon opening the project I am presented with an incomplete design, with just some connectors and a button and the audio (I guess the I2S) components with no routing. I spent the better part of yesterday attempting to fill in the missing pieces but was unsuccessful, mostly due to the fact that I'm a newb with Vivado, the ZYNQ FPGA and the 7020 dev board.

In the readme it states that it is provided 'as is' and no further development to newer version of the board will be maintained.

This is disappointing for a few reasons, the main one being I have no starting point to peruse the functionality of the board in general with associated working code. By playing around with the board I found in addition to the leds putting on a light show, there is audio out of the headphone jack and the buttons and switches have other functionality. From the OOB code I can see references to the HDMI and DVI, although I haven't hooked up a monitor to it to see if there is anything actually happening there. Another reason is in case I brick the board, which I'm bound to do at least at first, I will have a known working set of modules to reload to get back to 'square one'. Lastly, having working code and playing around with it is the best way, for me, to learn about a system.

Does anyone know of any other course to obtain the OOB code?

[JColvin]

Hi @ArKay99,

I'm not in the office to check this for certain, but offhand I would guess that the out of the box demo you downloaded from the Zybo Z7 Resource Center does not include all of the necessary materials in the .zip. I'll double check this and make sure it gets updated tomorrow. What you can try in the meantime is the HDMI demo project that is in the example projects above the additional resources section for another demo that doesn't require some additional hardware that you might not have ready access to.

Thanks,
JColvin

[ArKay99]

Thank you JColvin. I wasn't expecting a response on father's day, so double thanks. An FYI, I hooked up an HDMI monitor and there is a test pattern being tx. I haven't checked the rx. I'll wait for your response tomorrow. In the meantime I'm going to see how to download the bitstream from the Zybo to a file on my computer, just so I at least have that.

[JColvin]

Hi @ArKay99,

I ran the project as is from the downloaded file as on Vivado 2016.4 and it generated with no errors and everything looks as it should. I was also able to have it generate a bitstream successfully as well and launch on SDK as well.

What commands did you use to create the project? In the readme there is a small typo when running the create_project script. I don't know if you corrected it already but the correct formatting is as follows (modified for the path of where I stored my project when I ran it for the Zybo Z7-20):

cd C:/Users/jcolvin/Documents/VivadoPrj/zybo_z7_bist/z20/demo/proj/
source ./create_project.tcl

Did you do the same for your project? I'm guessing that you have the Zybo Z7-20 board based on your previous thread, though I don't know that for certain.

As for reading a bitstream from an FPGA after it's programmed onto it, those of us at Digilent haven't done that, but there are a few threads about it here, here, and here.

Thanks,
JColvin

[ArKay99]

Thank you for verifying the project creation script. Yes, I had done what you did. I also ran it without the "./" prepended and got the same results. However, what I did notice was your path to the .tcl file and mine were different in that none of your directories had a space in the name. I had my projects in a folder named Xilinx Projects. I could cd to it using the old DOS trick of putting quotes around the path. Apparently tcl has problems internally when operating on folders with a space in the name. I admitted I am a newb. I made a new directory without a space, extracted the zip to that folder, opened Vivado 2016.4, cd'ed to the project directory and ran the script with the ./ . Now I have a working project to explore. I can't thank you enough.

Yes, I have the ZYBO Z7-20.

I will look into those threads.