I am a beginner of ethernet design. I got a small project published on this website: http://www.fpga4fun.com/10BASE-T0.html . I have successfully updated MAC address, IP, etc... But I have noidea how to set constraint file in ISE.
Through reading the Nexys 4 DDR manual, I guess I need an extra clkIn for this project to work on the board, so I created two clocks: one is for D5, CLKIN, 50MHz, and another is for the project, 20MHz. and I set the pin number in the project below.
NET "clk" LOC = "E3" | IOSTANDARD = "LVCMOS33"; NET "clk" TNM_NET = sys_clk_pin;
NET "Ethernet_TDp" LOC=A9 | IOSTANDARD=LVCMOS33; NET "Ethernet_TDm" LOC=C9 | IOSTANDARD=LVCMOS33;
A9 is connected to MDIO, and C9 is connected to MDC. But I cannot see any data flow from PC to the board using the software provided by that website.
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mikuru
Hi,
I am a beginner of ethernet design. I got a small project published on this website: http://www.fpga4fun.com/10BASE-T0.html . I have successfully updated MAC address, IP, etc... But I have no idea how to set constraint file in ISE.
Through reading the Nexys 4 DDR manual, I guess I need an extra clkIn for this project to work on the board, so I created two clocks: one is for D5, CLKIN, 50MHz, and another is for the project, 20MHz. and I set the pin number in the project below.
NET "clk" LOC = "E3" | IOSTANDARD = "LVCMOS33";
NET "clk" TNM_NET = sys_clk_pin;
NET "Ethernet_TDp" LOC=A9 | IOSTANDARD=LVCMOS33;
NET "Ethernet_TDm" LOC=C9 | IOSTANDARD=LVCMOS33;
A9 is connected to MDIO, and C9 is connected to MDC. But I cannot see any data flow from PC to the board using the software provided by that website.
Can anyone help me set the constraint file?
Thank you!
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