Valentin Posted June 14, 2018 Share Posted June 14, 2018 HI. I try simulate ISERDESE2. But it doesn't work. Below my code: ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; library UNISIM; use UNISIM.Vcomponents.ALL; entity CLK_DAC is Port ( CLK_200MHz_P : in STD_LOGIC; CLK_200MHz_N : in STD_LOGIC; DCO_P : in STD_LOGIC; DCO_N : in STD_LOGIC; RESET : in STD_LOGIC; DATA_P : in STD_LOGIC; DATA_N : in STD_LOGIC; DATA_Sample0 : out STD_LOGIC_VECTOR(7 downto 0); Serial_out : out STD_LOGIC; TXCLK : out STD_LOGIC; TXCLKDIV : out STD_LOGIC); end CLK_DAC; architecture RTL of CLK_DAC is signal DCO_ibugds : std_logic; signal Data_ibufds : std_logic; signal CLK_IDelay : std_logic; signal CLK200MHZ_IBUFGDS : std_logic; signal CLK200_BUFG : std_logic; signal CLK_bufio : std_logic; signal CLK_bufr : std_logic; signal CLKB : std_logic; signal arAcqData : std_logic_vector(7 downto 0); signal Comb_out : std_logic; begin ---------------------------------------------------------------------------------- IBUFGDS_DCO_AD9430 : IBUFGDS port map ( O => DCO_ibugds, I => DCO_P, IB => DCO_N ); BUFIO_inst : BUFIO port map ( O => CLK_bufio, -- 1-bit output: Clock output (connect to I/O clock loads). I => DCO_ibugds -- 1-bit input: Clock input (connect to an IBUF or BUFMR). ); BUFR_inst : BUFR generic map ( BUFR_DIVIDE => "4" -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8" ) port map ( O => CLK_bufr, -- 1-bit output: Clock output port CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only) CLR => '0', -- 1-bit input: Active high, asynchronous clear (Divided modes only) I => DCO_ibugds -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect ); TXCLKDIV <= CLK_bufr; TXCLK <= CLK_bufio; ---------------------------------------------------------------------------- IBUFGDS_DATA_AD9430 : IBUFDS port map ( O => Data_ibufds, I => DATA_P, IB => DATA_N ); CLKB <= not CLK_bufio; ISERDESE2_inst : ISERDESE2 generic map ( DATA_RATE => "DDR", -- DDR, SDR DATA_WIDTH => 8, -- Parallel data width (2-8,10,14) DYN_CLKDIV_INV_EN => "FALSE", -- Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE) DYN_CLK_INV_EN => "FALSE", -- Enable DYNCLKINVSEL inversion (FALSE, TRUE) -- INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1) INIT_Q1 => '0', INIT_Q2 => '0', INIT_Q3 => '0', INIT_Q4 => '0', INTERFACE_TYPE => "NETWORKING", -- MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE IOBDELAY => "NONE", -- NONE, BOTH, IBUF, IFD NUM_CE => 2, -- Number of clock enables (1,2) OFB_USED => "FALSE", -- Select OFB path (FALSE, TRUE) SERDES_MODE => "MASTER", -- MASTER, SLAVE -- SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1) SRVAL_Q1 => '0', SRVAL_Q2 => '0', SRVAL_Q3 => '0', SRVAL_Q4 => '0' ) port map ( O => Comb_out, -- 1-bit output: Combinatorial output -- Q1 - Q8: 1-bit (each) output: Registered data outputs Q1 => arAcqData(0), Q2 => arAcqData(1), Q3 => arAcqData(2), Q4 => arAcqData(3), Q5 => arAcqData(4), Q6 => arAcqData(5), Q7 => arAcqData(6), Q8 => arAcqData(7), -- SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports SHIFTOUT1 => open, SHIFTOUT2 => open, BITSLIP => '0', -- 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to -- CLKDIV when asserted (active High). Subsequently, the data seen on the -- Q1 to Q8 output ports will shift, as in a barrel-shifter operation, one -- position every time Bitslip is invoked (DDR operation is different from -- SDR). -- CE1, CE2: 1-bit (each) input: Data register clock enable inputs CE1 => '1', CE2 => '1', CLKDIVP => '0', -- 1-bit input: TBD -- Clocks: 1-bit (each) input: ISERDESE2 clock input ports CLK => CLK_bufio, -- 1-bit input: High-speed clock CLKB => CLKB, -- 1-bit input: High-speed secondary clock CLKDIV => CLK_bufr, -- 1-bit input: Divided clock OCLK => '0', -- 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY" -- Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity DYNCLKDIVSEL => '0', -- 1-bit input: Dynamic CLKDIV inversion DYNCLKSEL => '0', -- 1-bit input: Dynamic CLK/CLKB inversion -- Input Data: 1-bit (each) input: ISERDESE2 data input ports D => Data_ibufds, -- 1-bit input: Data input DDLY => '0', -- 1-bit input: Serial data from IDELAYE2 OFB => '0', -- 1-bit input: Data feedback from OSERDESE2 OCLKB => '0', -- 1-bit input: High speed negative edge output clock RST => RESET, -- 1-bit input: Active high asynchronous reset -- SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports SHIFTIN1 => '0', SHIFTIN2 => '0' ); Serial_out <= Comb_out; DATA_Sample0 <= arAcqData; end RTL; Please tell me where I have a mistake! Thanks. Link to comment Share on other sites More sharing options...
hamster Posted June 14, 2018 Share Posted June 14, 2018 Humm.... DATA_P and DATA_N are not mirrors of each other. You might also need to delay DATA_P and DATA_N with respect to the clock signal, so it samples in the middle of the bit. Link to comment Share on other sites More sharing options...
Valentin Posted June 14, 2018 Author Share Posted June 14, 2018 2 hours ago, hamster said: Humm.... DATA_P and DATA_N are not mirrors of each other. You might also need to delay DATA_P and DATA_N with respect to the clock signal, so it samples in the middle of the bit. Yes, mistake in DATA_N. Thanks a lot. Link to comment Share on other sites More sharing options...
Question
Valentin
HI.
I try simulate ISERDESE2. But it doesn't work. Below my code:
---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; library UNISIM; use UNISIM.Vcomponents.ALL; entity CLK_DAC is Port ( CLK_200MHz_P : in STD_LOGIC; CLK_200MHz_N : in STD_LOGIC; DCO_P : in STD_LOGIC; DCO_N : in STD_LOGIC; RESET : in STD_LOGIC; DATA_P : in STD_LOGIC; DATA_N : in STD_LOGIC; DATA_Sample0 : out STD_LOGIC_VECTOR(7 downto 0); Serial_out : out STD_LOGIC; TXCLK : out STD_LOGIC; TXCLKDIV : out STD_LOGIC); end CLK_DAC; architecture RTL of CLK_DAC is signal DCO_ibugds : std_logic; signal Data_ibufds : std_logic; signal CLK_IDelay : std_logic; signal CLK200MHZ_IBUFGDS : std_logic; signal CLK200_BUFG : std_logic; signal CLK_bufio : std_logic; signal CLK_bufr : std_logic; signal CLKB : std_logic; signal arAcqData : std_logic_vector(7 downto 0); signal Comb_out : std_logic; begin ---------------------------------------------------------------------------------- IBUFGDS_DCO_AD9430 : IBUFGDS port map ( O => DCO_ibugds, I => DCO_P, IB => DCO_N ); BUFIO_inst : BUFIO port map ( O => CLK_bufio, -- 1-bit output: Clock output (connect to I/O clock loads). I => DCO_ibugds -- 1-bit input: Clock input (connect to an IBUF or BUFMR). ); BUFR_inst : BUFR generic map ( BUFR_DIVIDE => "4" -- Values: "BYPASS, 1, 2, 3, 4, 5, 6, 7, 8" ) port map ( O => CLK_bufr, -- 1-bit output: Clock output port CE => '1', -- 1-bit input: Active high, clock enable (Divided modes only) CLR => '0', -- 1-bit input: Active high, asynchronous clear (Divided modes only) I => DCO_ibugds -- 1-bit input: Clock buffer input driven by an IBUF, MMCM or local interconnect ); TXCLKDIV <= CLK_bufr; TXCLK <= CLK_bufio; ---------------------------------------------------------------------------- IBUFGDS_DATA_AD9430 : IBUFDS port map ( O => Data_ibufds, I => DATA_P, IB => DATA_N ); CLKB <= not CLK_bufio; ISERDESE2_inst : ISERDESE2 generic map ( DATA_RATE => "DDR", -- DDR, SDR DATA_WIDTH => 8, -- Parallel data width (2-8,10,14) DYN_CLKDIV_INV_EN => "FALSE", -- Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE) DYN_CLK_INV_EN => "FALSE", -- Enable DYNCLKINVSEL inversion (FALSE, TRUE) -- INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1) INIT_Q1 => '0', INIT_Q2 => '0', INIT_Q3 => '0', INIT_Q4 => '0', INTERFACE_TYPE => "NETWORKING", -- MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE IOBDELAY => "NONE", -- NONE, BOTH, IBUF, IFD NUM_CE => 2, -- Number of clock enables (1,2) OFB_USED => "FALSE", -- Select OFB path (FALSE, TRUE) SERDES_MODE => "MASTER", -- MASTER, SLAVE -- SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1) SRVAL_Q1 => '0', SRVAL_Q2 => '0', SRVAL_Q3 => '0', SRVAL_Q4 => '0' ) port map ( O => Comb_out, -- 1-bit output: Combinatorial output -- Q1 - Q8: 1-bit (each) output: Registered data outputs Q1 => arAcqData(0), Q2 => arAcqData(1), Q3 => arAcqData(2), Q4 => arAcqData(3), Q5 => arAcqData(4), Q6 => arAcqData(5), Q7 => arAcqData(6), Q8 => arAcqData(7), -- SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports SHIFTOUT1 => open, SHIFTOUT2 => open, BITSLIP => '0', -- 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to -- CLKDIV when asserted (active High). Subsequently, the data seen on the -- Q1 to Q8 output ports will shift, as in a barrel-shifter operation, one -- position every time Bitslip is invoked (DDR operation is different from -- SDR). -- CE1, CE2: 1-bit (each) input: Data register clock enable inputs CE1 => '1', CE2 => '1', CLKDIVP => '0', -- 1-bit input: TBD -- Clocks: 1-bit (each) input: ISERDESE2 clock input ports CLK => CLK_bufio, -- 1-bit input: High-speed clock CLKB => CLKB, -- 1-bit input: High-speed secondary clock CLKDIV => CLK_bufr, -- 1-bit input: Divided clock OCLK => '0', -- 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY" -- Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity DYNCLKDIVSEL => '0', -- 1-bit input: Dynamic CLKDIV inversion DYNCLKSEL => '0', -- 1-bit input: Dynamic CLK/CLKB inversion -- Input Data: 1-bit (each) input: ISERDESE2 data input ports D => Data_ibufds, -- 1-bit input: Data input DDLY => '0', -- 1-bit input: Serial data from IDELAYE2 OFB => '0', -- 1-bit input: Data feedback from OSERDESE2 OCLKB => '0', -- 1-bit input: High speed negative edge output clock RST => RESET, -- 1-bit input: Active high asynchronous reset -- SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports SHIFTIN1 => '0', SHIFTIN2 => '0' ); Serial_out <= Comb_out; DATA_Sample0 <= arAcqData; end RTL;
Please tell me where I have a mistake! Thanks.
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