AXI SPI on adrv9361z7035 (formerly PicoZed SDR)

[sbates]

I have a "PicoZED SDR" development kit.  We have heavily modified the demo project in order to prove that the AD9361 can do what we need.  At this stage we need to control an external SPI device.  I am trying to add an AXI SPI to the Xilinx project and get it to show up in Petalinux /dev.  I believe that I have got the AXI QSPI added into Vivado project and bitstream and devicetree.dtb created, but I am getting errors on the Linux boot log telling me that it failed to register the port.

I have read MANY examples and posts, but I am still very unsure (and obviously something is wrong) about the devicetree file and I'm not even 100% sure that I have properly added the AXI SPI to the Vivado project.  My SPI port should be at address 0x41e0000.  I can stop teh boot at uboot and probe around and the port seems to be there.

Below is my entry in the dts file.  I have so many questions about this I'm not even quite sure where to begin, but let me try:

1. Where should this entry be in the dts file?  I currently have it within the fpga-axi@0 {} block.  There are a bunch of other AXI devices listed there.
2. Many of the other AXI peripherals have "compatible="xlnx,axi..." but all of the examples I found for the SPI have "compatible="xlnx,xps-spi...".  What is the correct compatible string?
3. How can I tell which is the correct interrupt? 
4. Most examples have only 2 numbers in the interrupts <>, but some have 3.  Which is correct?
5. What is the correct clocks=<>?
6. Most examples and many forum posts talk about the need to have the correct clock-names.  How can I tell what are the correct clock names?  I used what I found in a number of examples and what I found in other places in my existing dts file for things that seem to be working.

Thank you,

Steve

u-boot> md.l 41e00060 1
41e0060: 00000180  <== default value of SPICR
u-boot> md.l 41e00064
41e00064: 000000a5  <== default value of SPISR

                axi_quad_spi_2@41e00000 {
                        compatible = "xlnx,xps-spi-2.00.b","xlnx,xps-spi-2.00.a";
                        #address-cells=<1>;
                        #size-cells=<0>;
                        interrupt-parent = <0x1>;
                        interrupts = <0x0 0x36 0x4>;
                        clocks = <0x2 0xf 0xf>;
                        clock-names = "axi", "ref";
                        reg = <0x41e00000 0x10000>;
                        num-cs = <0x1>;
                        fifo-size = <16>;
                        bits-per-word = <8>;
                        xlnx,family="zynq-7000";
                        xlnx,fifl-exist=<0x1>;
                        xlnx,num_ss_bits=<0x1>;
                        xlnx,num_transfer-bits=<0x8>;
                        xlnx,sck-ratio=<0x20>;

                        device@0 {
                                compatible="spidev";
                                reg=<0>;  //Chip Select 0
                                spi-max-frequency=<3125000>;
                        };

 

[jpeyron]

Hi @sbates,

Welcome to the forums. I have reached out to a more experience embedded linux engineer to see if they have any input for you. I would also suggest to reach out to Avnet and Analog Devices support as well.

thank you,

Jon

[sbobrowicz]

@sbates

1) Petalinux automatically generates device-tree nodes for all the IP blocks in your vivado block diagram after you use petalinux-config --get-hw-description to import the new hdf. You should then make changes to these automatically generated nodes in system-user.dtsi (in the project-spec/meta-user/... folder) by using "&<ip name in block diagram>" to add or override existing properties. You can find the automatically generated nodes in the pl.dtsi file in the components folder after petalinux-build has been run at least once (I actually think you can run "petalinux-build -c devicetree" if you only want to see the generated nodes after importing the HDF). Following this procedure has many benefits, including ensuring that the node was instantiated in the correct bus.

2,4,5) You should check out the device tree binding Documentation found here: https://github.com/Xilinx/linux-xlnx/tree/master/Documentation/devicetree/bindings . Make sure you are looking at the version of the code that is on a tag corresponding to your version of Petalinux (to make sure it matches up). You will find a lot of general information there about how a device tree should look, for example clock and interrupt bindings. You will also find a file there for each Xilinx driver that documents all optional and required properties. For example here is the doc for the SPI driver: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/spi/spi-xilinx.txt . The compatible string is the most important, it must match the documentation or the driver won't be loaded.

3,6) The automatically generated nodes in pl.dtsi should set the interrupts and clock related properties correctly. You can compare with the documentation linked above if you want to ensure they are being generated correctly.

[sbates]

@sbobrowicz

OK Thanks!  It looks like I don't have the PetaLinux build environment set up on my Vivado Box.  I am working through some tutorials on getting that setup and I will be back to you once I get that all setup and working.

I am getting the PetaLinux from this link:

https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-design-tools.html

I am using the 2017.1 (to match the dev kit FPGA project that works with the Version of Vivado I have).  Anyway, I am using the adrv9361z7035 dev kit, but the link above does not seen to have the correct BSP. Any Ideas?

 

Thank you,

Steve

[sbobrowicz]

You'll have to ask ADI (or the maker of the dev board) to make a BSP for you, or you will have to make the petalinux project yourself. UG1144 from Xilinx is the right place to start to learn how to create a Petalinux project from scratch. Make sure you use the version of that document that is targeted for 2017.1, it can change A LOT between releases.