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6 I2C Ports for DMA-Audio on the Nexys-Video board vs. 2 physical pins!!



There is a demo project for setting up Audio Codec on the Nexys Board here. After running the .tcl for project creation there are several problems:

1- The project is not compatible with Vivado 2017.4. I solved its many issues after several tries.

2- There are 6 I2C ports in the MicroBlaze block design for talking to the codec, whereas there should be 2 ports; i.e. SDA & SCL. When implementing design, BitGen fails for having no pin location for 6 I2C pins.

          Why such an error exist and how should I handle it?

          Note: I have designed an IO_BUF which connects 3 pins and makes an inout connection. One for SDA and one for SCL.

3- After bit file generation with mentioned workaround (Not sure it will work), hardware handoff is not generated by VIVADO. I have to generate it using custom tcl commands found in the xilinx documentations.


Please provide support for the mentioned problems.

A working project for such a demo is a must!



Edited by msjatdigilent

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Another problem: After forcing export to SDK, the SDK fails to program the FPGA, and says that there is no download.bit file.

Ther does exist a bit file, namely design_1.bit, but the SDK does not build download.bit by combining design_1.bit and application program!


Please help.

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Hi @msjatdigilent,

Vivado projects are version specific. This project was updated to be used in vivado 2016.4.  To use this project in a newer version of vivado i would suggest to start with a fresh project. Load the project into vivado 2017.4. Next upgrade/generate the ip cores by tools->reports->report ip status. Then create a wrapper. Next generate a bitstream. You then export hardware including the bitstream. Then launch sdk. Once sdk is loaded import the   DMAaudio and DMAaudio_bsp. If there are errors then right click on the DMAaudio_bsp and re-generate the bsp.  Please let us know if you are still having issues. 

thank you,


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