dvi2rgb IP v1.9 rev1 throws error [DRC PDRC-34] where v1.8 rev5 didn't

[joaBaur]

Hi,

I'm getting a route design error with a simple HDMI pass-through project using the Diligent "dvi2rgb" IP v1.9 rev1. The exact same block design using the previous dvi2rgb IP (v1.8 rev5) works, without errors...?

My Setup: Vivado 2018.1, ArtyZ7-20 board, IP: Diligent Github release "vivado-library-2016.4-1".

In this very basic block design there's only a Clocking Wizard IP (with "clk_in1" set to "sys clock" @ 125 MHz and "clk_out1" set to 200 MHz for the RefClk), and the "dvi2rgb" IP is directly connected to a "rgb2dvi" IP (v1.4 rev7). The "TDMS clock range" of the dvi2rgb IP is set to ">=120 MHz (1080p)".

Here's the sys_clock constraint:

set_property -dict { PACKAGE_PIN H16    IOSTANDARD LVCMOS33 } [get_ports { sys_clock }]; #IO_L13P_T2_MRCC_35 Sch=SYSCLK
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sys_clock }];

When I use the dvi2rgb v1.8 rev5 IP from the Diligent Github release "vivado-library-2015.4-3", the bitstream is generated and the HDMI pass-through works (no error, no critical warning). When I create the exact same block design from scratch using the dvi2rgb v1.9 rev1 IP from the Diligent Github release "vivado-library-2016.4-1", it throws this error:

Implementation > Route Design > DRC > Physical Configuration > PLLE2_ADV >
[DRC PDRC-43] PLL_adv_ClkFrequency_div_no_dclk: The computed value 1650.165 MHz (CLKIN1_PERIOD, net CLK) for the VCO operating frequency of the PLLE2_ADV site PLLE2_ADV_X1Y0 (cell Main_i/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/GenPLL.DVI_ClkGenerator) falls outside the operating range of the PLL VCO frequency for this device (800.000 - 1600.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input period CLKINx_PERIOD (6.059999), multiplication factor CLKFBOUT_MULT_F (10) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

So how can I get the dvi2rgb v1.9 IP to work, what is causing the error?

[elodg]

I just ran implementation on the Zybo-Z7-10-HDMI project and it completed bitstream generation. Don't throw me off the scent here!

So the implementation error is given for the PLL in rgb2dvi being out-of-range, because it is driven by a 165MHz PixelClk and it multiplies it by 10 internally, which is outside the 1600MHz maximum for PLL. PixelClk needs to be constrained properly for your maximum resolution. For 1080p, you are shooting for 148.5MHz. In a pass-through design this clock is coming from dvi2rgb, so you want to make sure that the TMDS input clock is constrained. Add

create_clock -period 6.734 -waveform {0 3.367} [get_ports { hdmi_in_clk_p }];

to your top-level XDC.

[JColvin]

Hi @joaBaur,

I have asked some other engineers much more experienced with the dvi2rgb IP core about this.

Thanks,
JColvin

[elodg]

@joaBaur,

I don't think this is related to the IP rev, but rather default settings for the expected TMDS clock frequency. From the documentation:

Quote

Error message during bitstream generation:

[DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 1650.165 MHz (CLKIN1_PERIOD, net CLK_IN_hdmi_clk) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X0Y0 (cell test_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (6.059999), multiplication factor CLKFBOUT_MULT_F (10.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

Solution: Adjust expected TMDS clock frequency higher in IP customization.

Also, 165MHz TMDS clock is way outside the Artix-7 FPGA's BUFIO/BUFR capabilities. You might want to lower that.

[joaBaur]

Quote

Solution: Adjust expected TMDS clock frequency higher in IP customization.

Well, as I wrote in my inital post:

Quote

The "TDMS clock range" of the dvi2rgb IP is set to ">=120 MHz (1080p)"

That's the highest setting via the IP customization.

Quote

Also, 165MHz TMDS clock is way outside the Artix-7 FPGA's BUFIO/BUFR capabilities. You might want to lower that.

Yes, I understand that this is where the error is coming from. But (as a FPGA beginner) I don't understand how I can/should do that besides of the IP customization dialog?

Quote

I don't think this is related to the IP rev

Well, I think it definitely is - I used the exact same settings and design with the v1.8 version and it throws no errors. Maybe the added ILA debug functions of the v1.9 rev have some side effects?

[icyman]

I have same problem. 

The div2rgb ip is needed to be check with Zybo-Z7-10-HDMI example.

 

[joaBaur]

Quote

create_clock -period 6.734 -waveform {0 3.367} [get_ports { hdmi_in_clk_p }];

Thank you so much, this made the error go away!

[varunb]

I tried creating a clock for the hdmi_in_clk_p pin, but it still threw the same error. Any ideas?

[jpeyron]

Hi @varunb,

It looks like you have received help on your other post here .

thank you,

Jon