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zybo, [Vivado 12-1411] Cannot set LOC property of ports, Site location is not valid ["C:/University_of_Toronto/2018summer/Ethernet_improve/UDP/top/top.srcs/constrs_1/new/master.xdc":62]



I am trying to develop Ethernet transmission with Zybo Z7-10.

I tried to add ports like eth_txctl to xdc file, but there is a critical warning I can't understand.

You can see pictures in attachments, the ports in my module, the ports I connect pin with, also the project settings.

I don't understand why vivado gives my critical warning that the pin is not valid.  If I try the ports eth_rxctl and connects it with pin D13, there would't be any warnings. 

I attached the schematic link as well, where I found the pins and port. 

I really don't get it, for example, the ports eth_txctl and eth_rxctl are literally on the same block in schematic. According to the schematics, I connect ports and pins, how come there is one work and

the other doesn't work?


Thanks a lot




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Hi @zengqin3,

Welcome to the forums. The zybo-Z7-10 has a zynq processor. The ethernet is directly connected to the Zynq processor. Here is a xilinx forum thread that discusses trying to use the ethernet through the pl.  I believe the PHY is connected to one of the PS MACs via RGMII. The MAC then drops the Ethernet frames via DMA to the RAM, from where it can be accessed by the ARM Cores.  If you configure the PSs I/O, you will find the option to route the Eth0 to the EMIO Bank, which would allow access from the PL side. If you do this i believe it will cut off the connection between MAC and PHY, giving the PL access only to the MAC via GMII, without any physical connection to the Ethernet port.  I also noticed in the messages from vivado it appears that you are using the Arty-S7-50 board file instead of the Zybo-Z7-10. I believe you would also need to add" IOSTANDARD LVCMOS33" to the xdc constraints in question to get ride of the xdc errors as well.

thank you,



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