I'm using two inferred RAM modules which are assigned an initial state by reading lines from a file, as suggested to me previously here, in VHDL. The setup works fine, and all the RAM contents are loaded during synthesis properly.
However, as my design is pretty large, it takes a lot of time to synthesize the project each time I need to only change the RAM initialization files. I need to synthesize very often while testing with different memory contents, my design being otherwise the same. Is there a way to only modify the memory contents of a design without having to synthesize the whole project? I tried using incremental builds but the improvement was not that effective.
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ntrstd11
I'm using two inferred RAM modules which are assigned an initial state by reading lines from a file, as suggested to me previously here, in VHDL. The setup works fine, and all the RAM contents are loaded during synthesis properly.
However, as my design is pretty large, it takes a lot of time to synthesize the project each time I need to only change the RAM initialization files. I need to synthesize very often while testing with different memory contents, my design being otherwise the same. Is there a way to only modify the memory contents of a design without having to synthesize the whole project? I tried using incremental builds but the improvement was not that effective.
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