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cgarry

Help with my Zybo HDMI to VGA Design

Question

I'm trying to develop a video pipeline on the Zybo platform that takes HDMI video in passes it to a custom IP and outputs the new video through VGA. I manage to create a system that takes HDMI and passes the video straight out the VGA interface but when I add in the AXI stream to video IP blocks in I can't seem to get a video out of the VGA. 

image.thumb.png.8184c1cf3875182b6bd71080f23871cd.png

I tried tying all the rst_n and enable on the vid_in_axi4s, axi4s_vid_out and tc off to one but still doesn't output any video on the VGA. I also output the locked signal from the axi4s_vid_out IP to one of the LEDs on the board and it never gets set high. Does anyone have any idea what I might have setup wrong or if I'm missing something?

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Hi Sergiu,

 

The "lock" signal is connected to the lock status of the DVI2RGB block while the "locked" is connected to the lock status of the AXIS to RGB block. Both are connected to LEDS but only the "lock" signal is asserted. I did some more debug and I can see the AXIS to RGB block is underflowing but it is receiving data from the RGB to AXIS block so I'm not sure why it is underflowing.

 

Regards,

 

Cathal

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The example used on the reference page isn't much good to me as loads the data into the DRAM. I want a system that just passes an image through a image processing block and back out again.

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The connection flow is the following:

Sink (Zybo) asserts Hot-Plug Detect -> confirm that HDMI_HPD is tied high and HDMI_OUT_EN is unused or tied low.

Source (whatever you have connected) queries the capabilities over DDC -> confirm that Digilent DVI appears as a secondary monitor on a PC for example.

Source begins transmitting video -> confirm that the Source actually enables the secondary monitor and drives a compatible resolution.

Sink locks onto the signal -> confirm that clk_wiz is locked and aPixelClkLckd goes high.

v_vid_in_axi4s splits video data into timing and AXI-Stream -> confirm with ILA that tvalid goes high and timing signals fit your resolution.

v_tc matches the timing signal to a known resolution and, if configured, re-generates the same timing on its output -> confirm with ILA.

v_axi4s_video_out waits for Start-of-Frame (tuser) and enables the generator in v_tc -> confirm vtg_ce and locked go high.

Video appears on VGA -> confirm hsync and vsync are correctly timed for the expected resolution.

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