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Jan Kok

How to add my own blocks with Vivado IP Integrator?

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I've gone through Getting Started with the Vivado IP Integrator https://reference.digilentinc.com/vivado/getting-started-with-ipi/start. Now I want to insert my own blocks into a block diagram, so I can create designs that use both the FPGA fabric and the on-chip ARM cores on my Arty Z7 board.

Below is a block diagram and the Verilog code for "myblock". I want to insert myblock in the connection between axi_gpio_1 and rgb_led so I can do some transformations on those signals. How can I determine the "data type" of the ports of axi_gpio_1 and rgb_led, and how can I modify myblock.v so its ports are compatible and I can connect myblock between axi_gpio_1 and rgb_led?

A more general question: what would you recommend as a next level of tutorial to study so that I wouldn't have to ask the questions above? I've looked on the Xilinx site, but the amount of documentation is overwhelming. I don't know where to start!

Here is myblock.v and part of my block diagram:LEDblock.thumb.png.070c37ce402785c72513bfac057b9f09.png

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Hi @Jan Kok,

When you make a custom ip core you dictate the inputs and outputs. For your block design i believe you would disconnect the bus connecting the gpio2 and the RGB's and connect the RGB's to the outbus of your myblock. You might also need to connect you myblock to gpio2_io_t instead of gpio2_io_o. 

For more learning for the Arty-z7 the Zynq book should be helpful. For hdl i would suggest fpga4fun and the  digital part of the learn site here. I do not have any suggestion besides our resource center for the arty for tutorial on microblaze.

thank you,

Jon

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The connection between axi_gpio_1 and rgb_led is a bundle of 3 busses: gpio2_io_i, gpio2_io_o, and gpio2_io_t. That is revealed by clicking on the "+" sign next to GPIO2 in the block diagram (in my screen shot, the + sign has turned into a - sign).

Since GPIO2 is a bundle and inbus is a simple bus, the bus structures don't match, and the block diagram editor won't let me connect them together, and for the same reason won't let me connect outbus with rgb_led. So one question is, how can I make myblock have ports that can be connected with axi_gpio_1 and rgb_led?

Another question is, how can I tell what the structure of the rgb_led input port is? There is no "+" sign that I can click on.

Thanks for the recommendations for more learning material. These look great. I'll start reading them.

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Hi @Jan Kok,

I reached out to a co-worker about this forum thread. They confirmed that you can dictate the type of output your custom block has.You should take a look at the Language Templates GUI. Under Verilog and IP Integrator HDL there is a set of macros you can add to your Verilog code to tell Vivado that a set of ports is actually an interface of a specific type with specific options. My co-worker also confirmed that you would disconnect the bus connecting the gpio2 and the RGB's and connect the RGB's to the outbus of your myblock. You might also need to connect you myblock to gpio2_io_t instead of gpio2_io_o.  They also stated that you can look at the "Design" tab in the pane that also contains "Sources". Under the External Interfaces dropdown, the rgb_leds interface shows up, and is a dropdown showing the signals contained in it.

33520982_10214495169966156_8852493411752607744_n.png?_nc_cat=0&oh=ea52da3e6b42533683ff4bae839c2d1b&oe=5B91806F


Also it's usually impossible to connect a full interface to multiple blocks. You should probably make the output pin of the expanded gpio interface external, and also connecting that pin to your own block requires that you do an xdc for the rgb leds.

thank you,

Jon

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Another approach that I generally favor is to add a few standard GPIO and or dual-port BRAM interfaces connected to IO in the board design and then have Vivado create an HDL for the whole board design. This HDL can then be instantiated as a component or module in a top level HDL of you own design. Adding additional functionality to the new top level is then ( more or less ) trivial. I'm not a fan of the IP integrator flow but I have created my own IP, mostly as an exercise in seeing what the costs are. Generally, I've found the effort to be more work than it's worth; and then there are Vivado version issues...

With the ZYNQ the board design flow is unavoidable but I've found that for me using the approach that I've just described reduces the anguish and frustration to manageable levels.

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Hi @zygot, thanks for sharing your thoughts on this subject.

I'm making some progress with getting myblock to work. Now I can connect it, but I'm getting some warnings and errors that I'm trying to resolve.

Another approach might be to modify an axi_gpio block, adding my own logic and removing stuff I don't need such as interrupt logic. That would be similar to what you mentioned (creating your own IP), except I would start with known working code rather than developing a new block from scratch.

What learning materials did you use to figure out how to make your own IP?

I do like the IP Integrator, mainly because the block diagram is much more compact (one page) and comprehensible compared with 1500 lines of Verilog in block_design.v.

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@Jan Kok,

If you feel comfortable using the approach that you have started with then I certainly don't want to discourage you from plugging ahead.

The first place to look for information is to fire up the Xilinx Documentation Navigator application installed with Vivado and look for application notes, User Guides and Tutorials. There are certainly a few describing how to create you own IP such as UG1118, UG1119, and UG896. 

It's been a while... but I did go through a 4 part lab series on creating IP but I haven't yet found them in my archives. I want to think that Digilent provided them.... but it may have been a distributor... Zedboard.org might be a place to go for step-by step tutorials. There is also a Xilinx user community forum. If I come across what I used I'll post a link to it here... though it might be pretty dated by now.

I get the allure of having a compact schematic picture of your system. I just don't feel the love or commitment from Vivado for my older IP design efforts... so, for the time being I'll hone my HDL speed-reading skills. 

Slogging though Xilinx script sourced HDL is certainly a daunting task... but once you develop a knack for figuring out how to locate the lines of interest it turns into a valuable skill. You'll have to trust me on this.

Edited by zygot

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It seems that the tutorial I was using was from the Xilinx University support page but is no longer available. If you google "creating Vivado IP tutorial" you might come up with something reasonably recent and useful. Best of luck.

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