Nexys 4 DDR - Pulse Width violation inside MIG

[party-pansen]

Hi,

a few days ago I started with Vivado 2015.3 and the digilent Board Files provided on this web site. I followed the example instructions for Microblaze setup, but I always get a pulse width error of -0.736ns as shown in the attached screenshot:

Is this a known Problem? Can anyone judge if it is critical and if yes how to solve it?

 

At some first tests accessing the memory everything seems to work fine...

 

Best regards

party-pansen

 

 

[JColvin]

Hi party-pansen,

I have asked some of our applications engineers about this; they'll get back to you here on the forum.

Thanks,
JColvin

[TommyK]

Hi party-panson,

This is a known problem, but it should not affect the design. The problem comes from the delay created when generating a 200MHz clock. It puts the MIG in another clock domain, which creates timing slack. It shouldn't a problem, but a fix would be to generate the 100MHz system clock with the MIG instead of the Clocking Wizard. This picture shows the clocking wizard generating a 200MHz clock going into the MIG, then a 100MHz clock coming out of the MIG.

 

Regards,

Tommy

[party-pansen]

Hi Tommy,

thanks for that information. I'll try this workaround with 200MHz input clock. Do I need to "hack" the mig controller to get this 100MHz output pin "ui_addn_clk_0" or will it be created automatically?

Regards

party-pansen

[TommyK]

Hi party-pansen,

Once you run the block automation for the MIG, you can double click on it and click "Next" until you see a checkbox to create additional clocks. This is where you'll create the 100MHz clock. You'll probably want to do this before running block automation on the Microblaze block as well, since there is an option to select the MIG generated 100MHz clock in the Microblaze block automation window. Let me know if you run into any problems!

 

Regards,

Tommy