• 0

Embedded Linux Tutorial


Question

Hi, im currently using Vivado 2018.1 on Ubuntu 16.04.3. Im doing the tutorial Embedded Linux Tutorial - Zybo. However, after running synthesis and implementation, im receiving these errors. Im new to the whole digilent, fpga and vivado thing. Sorry if i am unable to convey well enough in my message.

systemgenerate_target all [get_files  /home/deandre/zybo_base_system/source/vivado/hw/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/system.bd]
[BD 41-1348] Reset pin /axi_dispctrl_0/s_axi_aresetn (associated clock /axi_dispctrl_0/s_axi_aclk) is connected to asynchronous reset source /processing_system7_0/FCLK_RESET1_N.
This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /processing_system7_0/FCLK_CLK0.
ipx::edit_ip_in_project -upgrade true -name edit_myLed_v1_0 -directory /home/deandre/zybo_base_system/source/vivado/hw/ip_repo /home/deandre/zybo_base_system/source/vivado/hw/ip_repo/myLed_1.0/component.xml
[BD 41-1273] Error running can_apply_rule TCL procedure: ERROR: [Common 17-39] 'get_bd_intf_pins' failed due to earlier errors.
    ::bd::board_utils::is_intf_pin Line 3
[BD 5-104] A block design must be open to run this command. Please create/open a block design.
[#UNDEF] Tcl Error in evaluating proc can_apply_rule : ERROR: [Common 17-39] 'get_bd_intf_ports' failed due to earlier errors.
launch_runs impl_1 -to_step write_bitstream
[BD 41-1348] Reset pin /axi_dispctrl_0/s_axi_aresetn (associated clock /axi_dispctrl_0/s_axi_aclk) is connected to asynchronous reset source /processing_system7_0/FCLK_RESET1_N.
This may prevent design from meeting timing. Please add Processor System Reset module to create a reset that is synchronous to the associated clock source /processing_system7_0/FCLK_CLK0.
[BD 41-1356] Address block </myLed_0/S_AXI/S_AXI_reg> is not mapped into </processing_system7_0/Data>. Please use Address Editor to either map or exclude it.
Synthesis[Common 17-55] 'set_property' expects at least one object. ["/home/deandre/zybo_base_system/source/vivado/hw/zybo_bsd/zybo_bsd.srcs/constrs_1/new/base.xdc":1]
ImplementationDesign Initialization[Common 17-55] 'set_property' expects at least one object. ["/home/deandre/zybo_base_system/source/vivado/hw/zybo_bsd/zybo_bsd.srcs/constrs_1/new/base.xdc":1]
Place Design[Place 30-58] IO placement is infeasible. Number of unplaced terminals (8) is greater than number of available sites (0).
The following are banks with available pins:
 IO Group: 0 with : SioStd: LVCMOS18   VCCO = 1.8 Termination: 0  TermDir:  In   RangeId: 1  has only 0 sites available on device, but needs 8 sites.
    Term: BTNs_4Bits_tri_i[0]
    Term:  BTNs_4Bits_tri_i[1]
    Term:  BTNs_4Bits_tri_i[2]
    Term:  BTNs_4Bits_tri_i[3]
    Term:  SWs_4Bits_tri_i[0]
    Term:  SWs_4Bits_tri_i[1]
    Term:  SWs_4Bits_tri_i[2]
    Term:  and SWs_4Bits_tri_i[3]


[Place 30-374] IO placer failed to find a solution
Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve.

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|                                                                     IO Placement : Bank Stats                                                                           |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
| Id | Pins  | Terms |                               Standards                                |                IDelayCtrls               |  VREF  |  VCCO  |   VR   | DCI |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|  0 |     0 |     0 |                                                                        |                                          |        |        |        |     |
| 13 |     0 |     0 |                                                                        |                                          |        |        |        |     |
| 34 |    50 |     6 | LVCMOS33(6)                                                            |                                          |        |  +3.30 |    YES |     |
| 35 |    50 |    32 | LVCMOS33(24)  TMDS_33(8)                                               |                                          |        |  +3.30 |    YES |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+
|    |   100 |    38 |                                                                        |                                          |        |        |        |     |
+----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+

IO Placement:
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| BankId |             Terminal | Standard        | Site                 | Pin                  | Attributes           |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 34     | AC_MCLK              | LVCMOS33        | IOB_X0Y0             | T19                  |                      |
|        | AC_MUTE_N[0]         | LVCMOS33        | IOB_X0Y3             | P18                  |                      |
|        | BLUE_O[0]            | LVCMOS33        | IOB_X0Y21            | P20                  |                      |
|        | GREEN_O[1]           | LVCMOS33        | IOB_X0Y22            | N20                  |                      |
|        | HSYNC_O              | LVCMOS33        | IOB_X0Y23            | P19                  |                      |
|        | VSYNC_O              | LVCMOS33        | IOB_X0Y49            | R19                  |                      |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+
| 35     | HDMI_CLK_P           | TMDS_33         | IOB_X0Y74            | H16                  |                      |
|        | HDMI_CLK_N           | TMDS_33         | IOB_X0Y73            | H17                  |                      |
|        | HDMI_D0_P            | TMDS_33         | IOB_X0Y92            | D19                  |                      |
|        | HDMI_D0_N            | TMDS_33         | IOB_X0Y91            | D20                  |                      |
|        | HDMI_D1_P            | TMDS_33         | IOB_X0Y98            | C20                  |                      |
|        | HDMI_D1_N            | TMDS_33         | IOB_X0Y97            | B20                  |                      |
|        | HDMI_D2_P            | TMDS_33         | IOB_X0Y96            | B19                  |                      |
|        | HDMI_D2_N            | TMDS_33         | IOB_X0Y95            | A20                  |                      |
|        | AC_BCLK[0]           | LVCMOS33        | IOB_X0Y75            | K18                  |                      |
|        | AC_PBLRC[0]          | LVCMOS33        | IOB_X0Y77            | L17                  |                      |
|        | AC_RECLRC[0]         | LVCMOS33        | IOB_X0Y83            | M18                  |                      |
|        | AC_SDATA_I           | LVCMOS33        | IOB_X0Y76            | K17                  |                      |
|        | AC_SDATA_O[0]        | LVCMOS33        | IOB_X0Y84            | M17                  |                      |
|        | BLUE_O[1]            | LVCMOS33        | IOB_X0Y85            | M20                  |                      |
|        | BLUE_O[2]            | LVCMOS33        | IOB_X0Y80            | K19                  |                      |
|        | BLUE_O[3]            | LVCMOS33        | IOB_X0Y72            | J18                  |                      |
|        | BLUE_O[4]            | LVCMOS33        | IOB_X0Y64            | G19                  |                      |
|        | GREEN_O[0]           | LVCMOS33        | IOB_X0Y71            | H18                  |                      |
|        | GREEN_O[2]           | LVCMOS33        | IOB_X0Y82            | L19                  |                      |
|        | GREEN_O[3]           | LVCMOS33        | IOB_X0Y79            | J19                  |                      |
|        | GREEN_O[4]           | LVCMOS33        | IOB_X0Y65            | H20                  |                      |
|        | GREEN_O[5]           | LVCMOS33        | IOB_X0Y69            | F20                  |                      |
|        | HDMI_OEN[0]          | LVCMOS33        | IOB_X0Y87            | F17                  | *                    |
|        | RED_O[0]             | LVCMOS33        | IOB_X0Y86            | M19                  |                      |
|        | RED_O[1]             | LVCMOS33        | IOB_X0Y81            | L20                  |                      |
|        | RED_O[2]             | LVCMOS33        | IOB_X0Y66            | J20                  |                      |
|        | RED_O[3]             | LVCMOS33        | IOB_X0Y63            | G20                  |                      |
|        | RED_O[4]             | LVCMOS33        | IOB_X0Y70            | F19                  |                      |
|        | led[0]               | LVCMOS33        | IOB_X0Y54            | M14                  |                      |
|        | led[1]               | LVCMOS33        | IOB_X0Y53            | M15                  |                      |
|        | led[2]               | LVCMOS33        | IOB_X0Y99            | G14                  |                      |
|        | led[3]               | LVCMOS33        | IOB_X0Y93            | D18                  |                      |
+--------+----------------------+-----------------+----------------------+----------------------+----------------------+

[Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
[Common 17-69] Command failed: Placer could not place all instances

 

Link to post
Share on other sites

3 answers to this question

Recommended Posts

  • 0

Hi @DeAndreHJ,

I would suggest to use a newer project with a petalinux bsp. The newer projects have more functionality improvements. Also Petalinux is mainly a wrapper for yocto.  Here is the Petalinux Support for Digilent Boards which has a zybo bps in 2017.2 and 2017.4. The read me has a Quick-Start Guide for getting these projects up and going. In regards to you errors did you manually connect the signal pin reset to the resetn input of the clk_wiz_1 block. 

thank you,

Jon

Link to post
Share on other sites
  • 0

hi, i did not manually connect the signal pins resetn input of the clk_wiz_1block. However, i do recall that there wasnt any auto block connection, so, i connected some components following the scehmatics available in the tutorial.

Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now