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aarvy

Basys3. How to interface Analog Sensor and Servo motor?

Question

Hello all,

 

Can anyone help me in Basys 3 project? I am trying to  interface Analog Sensor to Basys3 XADC pin. I am trying to use the sample code given wiki basys3.

 

Priority:

1) Where do we change in given code for any specific XADC pin. I could not find any 'pin' definition in behavior code. Why there are some IP code files there? It is not UART though. 

2) How to generate PWM for Servo motor?

 

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Hi Arvy,

I don't want to put you wrong on the answer to qn 1, but the pins should be defined in the board's XDC file: You can find this on the product page at https://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1288&Prod=BASYS3

 

...
##Pmod Header JXADC
##Sch name = XA1_P
#set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
##Sch name = XA2_P
#set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
##Sch name = XA3_P
#set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
##Sch name = XA4_P
#set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
##Sch name = XA1_N
#set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
##Sch name = XA2_N
#set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
##Sch name = XA3_N
#set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
##Sch name = XA4_N
#set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]                
    #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
....
 
2) Driving a servo is relatively easy. You need a positive pulse of between 1ms and 2ms every 20ms. This can be done with a counter, and can be made easy by looking at the problem slightly differently. Here's some pseudo code for the HDL that needs to run every time the clock ticks:
if counter = CLOCK_FREQ_IN_MHz/50-1) then
  counter = 0;
else
  counter = counter + 1;
end if

if counter = CLOCK_FREQ_IN_MHz * 49/50 then
  servo_pin = '1';
else if counter = (setting * CLOCK_FREQ_IN_MHz) / (1000 * MAX_SETTING) then
  servo_pin = '0';
end if

Converted this to a suitable HDL this should generate the required pulse on servo_pin.

A good idea would be to separate this into two distinct testable parts. The first part might be to change the servo position using the switches on the board, the second to display the ADC reading on the LEDs. Once both parts are working independently you then connect them together and have your end design.

Edited by hamster

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Hi Hamster,

 

Thank you. I shall try servo code soon. Seems efficient. :)

For q1, I meant for top level code. We still need to define/use in top level code, I knew about XADC. But how do we connect both of them? I mean what the variable name to use ADC Channel 0 in given file?

 

I saw your wiki page on PmodAD1. How did you use ADC on JA. I thought we have only XADC jumpers for ADC!

 

Thank you.

 

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Hi, 

I used an external ADC PMOD on that project (have a look for PmodAD1 - http://www.digilentinc.com/Products/Detail.cfm?Prod=PMOD-AD1 ). 

Page 17 & 18 of http://www.digilentinc.com/Data/Products/BASYS3/Basys3_rm.pdf details how the PMOD ports are connected to the FPGA. The XADC user guide (http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf) is worth while reading too.

When you use the XADC, you have to connect your external pins (defined in the XDC file, and your top level design) to the correct connection on the XADC instance in your design. If you fail to do this the Place&Route process will fail.

Getting these Hard IP blocks (e.g. XADC, transceivers, Memory controllers, PCIe enponts) to work is very painful the first time. The next time you know what you need to do, making it much easier.

Mike

 

 

Edited by hamster

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Hi Arvy,

Here is some code I wrote tonight. It includes the XADC instance, set to measure channel 6 in unipolar mode.

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity xadc_test is
    Port ( clk100   : in  STD_LOGIC;
           led   : out STD_LOGIC_VECTOR (15 downto 0);
           JXADC : in  STD_LOGIC_VECTOR (7 downto 0));
end xadc_test;
architecture Behavioral of xadc_test is
    signal reading : std_logic_vector(15 downto 0) := (others => '0');
    signal muxaddr : std_logic_vector( 4 downto 0) := (others => '0');
    signal channel : std_logic_vector( 4 downto 0) := (others => '0');
    signal vauxn   : std_logic_vector(15 downto 0) := (others => '0');
    signal vauxp   : std_logic_vector(15 downto 0) := (others => '0');
begin
    led <= reading;
    -----------------------------------
    -- Pass through the analogue inputs
    -----------------------------------
    vauxp(6)  <= jxadc(0);  vauxn(6)  <= jxadc(4);
    vauxp(14) <= jxadc(1);  vauxn(14) <= jxadc(5);
    vauxp(7)  <= jxadc(2);  vauxn(7)  <= jxadc(6);
    vauxp(15) <= jxadc(3);  vauxn(15) <= jxadc(7);
     
XADC_inst : XADC generic map (
      -- INIT_40 - INIT_42: XADC configuration registers
      INIT_40 => X"9000", -- averaging of 16 selected for external channels
      INIT_41 => X"2ef0", -- Continuous Seq Mode, Disable unused ALMs, Enable calibration
      INIT_42 => X"0800", -- ACLK = DCLK/8 = 100MHz / 8 = 12.5 MHz 
      -- INIT_48 - INIT_4F: Sequence Registers
      INIT_48 => X"4701", -- CHSEL1 - enable Temp VCCINT, VCCAUX, VCCBRAM, and calibration
      INIT_49 => X"000CC", -- CHSEL2 - enable aux analog channels 6,7,14,15
      INIT_4A => X"0000", -- SEQAVG1 disabled all channels
      INIT_4B => X"0000", -- SEQAVG2 disabled all channels
      INIT_4C => X"0000", -- SEQINMODE0 - all channels unipolar
      INIT_4D => X"00CC", -- SEQINMODE1 - all channels unipolar
      INIT_4E => X"0000", -- SEQACQ0 - No extra settling time all channels
      INIT_4F => X"0000", -- SEQACQ1 - No extra settling time all channels
      -- INIT_50 - INIT_58, INIT5C: Alarm Limit Registers
      INIT_50 => X"b5ed", -- Temp upper alarm trigger 85°C
      INIT_51 => X"5999", -- Vccint upper alarm limit 1.05V
      INIT_52 => X"A147", -- Vccaux upper alarm limit 1.89V
      INIT_53 => X"dddd", -- OT upper alarm limit 125°C - see Thermal Management
      INIT_54 => X"a93a", -- Temp lower alarm reset 60°C
      INIT_55 => X"5111", -- Vccint lower alarm limit 0.95V
      INIT_56 => X"91Eb", -- Vccaux lower alarm limit 1.71V
      INIT_57 => X"ae4e", -- OT lower alarm reset 70°C - see Thermal Management
      INIT_58 => X"5999", -- VCCBRAM upper alarm limit 1.05V
      INIT_5C => X"5111", -- VCCBRAM lower alarm limit 0.95V
      -- Simulation attributes: Set for proper simulation behavior
      SIM_DEVICE       => "7SERIES",    -- Select target device (values)
      SIM_MONITOR_FILE => "design.txt"  -- Analog simulation data file name
   ) port map (
      -- ALARMS: 8-bit (each) output: ALM, OT
      ALM          => open,             -- 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram
      OT           => open,             -- 1-bit output: Over-Temperature alarm
      -- STATUS: 1-bit (each) output: XADC status ports
      BUSY         => open,             -- 1-bit output: ADC busy output
      CHANNEL      => channel,          -- 5-bit output: Channel selection outputs
      EOC          => open,             -- 1-bit output: End of Conversion
      EOS          => open,             -- 1-bit output: End of Sequence
      JTAGBUSY     => open,             -- 1-bit output: JTAG DRP transaction in progress output
      JTAGLOCKED   => open,             -- 1-bit output: JTAG requested DRP port lock
      JTAGMODIFIED => open,             -- 1-bit output: JTAG Write to the DRP has occurred
      MUXADDR      => muxaddr,          -- 5-bit output: External MUX channel decode
      
      -- Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0]
      VAUXN        => vauxn,            -- 16-bit input: N-side auxiliary analog input
      VAUXP        => vauxp,            -- 16-bit input: P-side auxiliary analog input
      
      -- CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs
      CONVST       => '0',              -- 1-bit input: Convert start input
      CONVSTCLK    => '0',              -- 1-bit input: Convert start input
      RESET        => '0',              -- 1-bit input: Active-high reset
      
      -- Dedicated Analog Input Pair: 1-bit (each) input: VP/VN
      VN           => '0', -- 1-bit input: N-side analog input
      VP           => '0', -- 1-bit input: P-side analog input
      
      -- Dynamic Reconfiguration Port (DRP) -- hard set to read channel 6 (XADC4/XADC0)
      DO           => reading,
      DRDY         => open,
      DADDR        => "0010110",  -- The address for reading AUX channel 6
      DCLK         => clk100,
      DEN          => '1',
      DI           => (others => '0'),
      DWE          => '0'
   );
end Behavioral;
And here is the XDC file for the Basys3:
set_property PACKAGE_PIN W5 [get_ports clk100]                            
    set_property IOSTANDARD LVCMOS33 [get_ports clk100]
    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk100]
## LEDs
set_property PACKAGE_PIN U16 [get_ports {led[0]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U15 [get_ports {led[5]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property PACKAGE_PIN U14 [get_ports {led[6]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property PACKAGE_PIN V14 [get_ports {led[7]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
set_property PACKAGE_PIN V13 [get_ports {led[8]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
set_property PACKAGE_PIN V3 [get_ports {led[9]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
set_property PACKAGE_PIN W3 [get_ports {led[10]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
set_property PACKAGE_PIN U3 [get_ports {led[11]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
set_property PACKAGE_PIN P3 [get_ports {led[12]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
set_property PACKAGE_PIN N3 [get_ports {led[13]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
set_property PACKAGE_PIN P1 [get_ports {led[14]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
set_property PACKAGE_PIN L1 [get_ports {led[15]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
##Pmod Header JXADC
##Sch name = XA1_P
set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]                
    set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
##Sch name = XA2_P
set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]                
    set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
##Sch name = XA3_P
set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]                
    set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
##Sch name = XA4_P
set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]                
    set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
##Sch name = XA1_N
set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]                
    set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
##Sch name = XA2_N
set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]                
    set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
##Sch name = XA3_N
set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]                
    set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
##Sch name = XA4_N
set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]                
    set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]

When downloaded to your board, the value displayed in binary on the the LEDs should reflect the voltage on Pin 0 if the PXADC. I tested just by pushing some header pins into the PMOD and touching the pin - not exactly a complete test, but enough to show that it does something.

NOTE: THE FULL SCALE VOLTAGE FOR THE XADC IS 1V, so some crafty planning might be required to interface to it.

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Hi,

Thank you. This looks really promising.  I shall try it soon.

Can't we use 3.3 V analog reference voltage rather than 1 V? Is it the limitation?

 

As per the above code, 'reading' is the variable for the input data then I can map this value to servo input. Am i right?

I mean, can we map this 'reading' as width of pulse for PWM -Servo motor? 

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Yes, in that design the DO port on the XADC signal is hard-wired to show the conversion of the ADC's AUX 6 channel, which is the XADC PMOD's pins 0 and 4.

I've connected that to a signal called "reading", which should have the result of the ADC conversion, updated every time the XADC's inbuilt sequencer performs a conversion on that channel.

To get an input that is in range, you have a few options.

Put a 3.3:1 voltage divider on the signal you are using (e.g. a   input ----|2.2K|--+--|1.0K|--- Gnd, and connect the ADC where the + sign is). This would only work well if the signal being measured has a relatively low output impedance (less than approx 300 Ohm).

If you are using a variable resistor, option 2 would be:


Vcc -----|2.2k |------| 1K Variable resistor| ----- Gnd

If you connect the variable resistor's wiper output to the ADC it should be swing from around 1.1V to 0V.

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Hi Hamaster,

 

Thank you. It worked thought there were some LEDs ON during zero voltage. I will fix it though. This is a nice way to monitor temperature and control Alarm. I know Hardware way to cut down the Voltage using voltage divider circuit, I just do not know Programming way to control Analog Reference for ADC.

 

I think we can use this reading in servo code to control the width of the Pulse. Can't we? We can just use a 'reading' as a 'counter' in below code or may be by mapping 'reading' to 'counter'.

 

if counter = CLOCK_FREQ_IN_MHz/50-1) then
  counter = 0;
else
  counter = counter + 1;
end if

if counter = CLOCK_FREQ_IN_MHz * 49/50 then
  servo_pin = '1';
else if counter = (setting * CLOCK_FREQ_IN_MHz) / (1000 * MAX_SETTING) then
  servo_pin = '0';
end if

 

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On November 30, 2015 at 1:59 AM, hamster said:

Hi Arvy,

Here is some code I wrote tonight. It includes the XADC instance, set to measure channel 6 in unipolar mode.

 

 


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity xadc_test is
    Port ( clk100   : in  STD_LOGIC;
           led   : out STD_LOGIC_VECTOR (15 downto 0);
           JXADC : in  STD_LOGIC_VECTOR (7 downto 0));
end xadc_test;
architecture Behavioral of xadc_test is
    signal reading : std_logic_vector(15 downto 0) := (others => '0');
    signal muxaddr : std_logic_vector( 4 downto 0) := (others => '0');
    signal channel : std_logic_vector( 4 downto 0) := (others => '0');
    signal vauxn   : std_logic_vector(15 downto 0) := (others => '0');
    signal vauxp   : std_logic_vector(15 downto 0) := (others => '0');
begin
    led <= reading;
    -----------------------------------
    -- Pass through the analogue inputs
    -----------------------------------
    vauxp(6)  <= jxadc(0);  vauxn(6)  <= jxadc(4);
    vauxp(14) <= jxadc(1);  vauxn(14) <= jxadc(5);
    vauxp(7)  <= jxadc(2);  vauxn(7)  <= jxadc(6);
    vauxp(15) <= jxadc(3);  vauxn(15) <= jxadc(7);
     
XADC_inst : XADC generic map (
      -- INIT_40 - INIT_42: XADC configuration registers
      INIT_40 => X"9000", -- averaging of 16 selected for external channels
      INIT_41 => X"2ef0", -- Continuous Seq Mode, Disable unused ALMs, Enable calibration
      INIT_42 => X"0800", -- ACLK = DCLK/8 = 100MHz / 8 = 12.5 MHz 
      -- INIT_48 - INIT_4F: Sequence Registers
      INIT_48 => X"4701", -- CHSEL1 - enable Temp VCCINT, VCCAUX, VCCBRAM, and calibration
      INIT_49 => X"000CC", -- CHSEL2 - enable aux analog channels 6,7,14,15
      INIT_4A => X"0000", -- SEQAVG1 disabled all channels
      INIT_4B => X"0000", -- SEQAVG2 disabled all channels
      INIT_4C => X"0000", -- SEQINMODE0 - all channels unipolar
      INIT_4D => X"00CC", -- SEQINMODE1 - all channels unipolar
      INIT_4E => X"0000", -- SEQACQ0 - No extra settling time all channels
      INIT_4F => X"0000", -- SEQACQ1 - No extra settling time all channels
      -- INIT_50 - INIT_58, INIT5C: Alarm Limit Registers
      INIT_50 => X"b5ed", -- Temp upper alarm trigger 85°C
      INIT_51 => X"5999", -- Vccint upper alarm limit 1.05V
      INIT_52 => X"A147", -- Vccaux upper alarm limit 1.89V
      INIT_53 => X"dddd", -- OT upper alarm limit 125°C - see Thermal Management
      INIT_54 => X"a93a", -- Temp lower alarm reset 60°C
      INIT_55 => X"5111", -- Vccint lower alarm limit 0.95V
      INIT_56 => X"91Eb", -- Vccaux lower alarm limit 1.71V
      INIT_57 => X"ae4e", -- OT lower alarm reset 70°C - see Thermal Management
      INIT_58 => X"5999", -- VCCBRAM upper alarm limit 1.05V
      INIT_5C => X"5111", -- VCCBRAM lower alarm limit 0.95V
      -- Simulation attributes: Set for proper simulation behavior
      SIM_DEVICE       => "7SERIES",    -- Select target device (values)
      SIM_MONITOR_FILE => "design.txt"  -- Analog simulation data file name
   ) port map (
      -- ALARMS: 8-bit (each) output: ALM, OT
      ALM          => open,             -- 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram
      OT           => open,             -- 1-bit output: Over-Temperature alarm
      -- STATUS: 1-bit (each) output: XADC status ports
      BUSY         => open,             -- 1-bit output: ADC busy output
      CHANNEL      => channel,          -- 5-bit output: Channel selection outputs
      EOC          => open,             -- 1-bit output: End of Conversion
      EOS          => open,             -- 1-bit output: End of Sequence
      JTAGBUSY     => open,             -- 1-bit output: JTAG DRP transaction in progress output
      JTAGLOCKED   => open,             -- 1-bit output: JTAG requested DRP port lock
      JTAGMODIFIED => open,             -- 1-bit output: JTAG Write to the DRP has occurred
      MUXADDR      => muxaddr,          -- 5-bit output: External MUX channel decode
      
      -- Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0]
      VAUXN        => vauxn,            -- 16-bit input: N-side auxiliary analog input
      VAUXP        => vauxp,            -- 16-bit input: P-side auxiliary analog input
      
      -- CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs
      CONVST       => '0',              -- 1-bit input: Convert start input
      CONVSTCLK    => '0',              -- 1-bit input: Convert start input
      RESET        => '0',              -- 1-bit input: Active-high reset
      
      -- Dedicated Analog Input Pair: 1-bit (each) input: VP/VN
      VN           => '0', -- 1-bit input: N-side analog input
      VP           => '0', -- 1-bit input: P-side analog input
      
      -- Dynamic Reconfiguration Port (DRP) -- hard set to read channel 6 (XADC4/XADC0)
      DO           => reading,
      DRDY         => open,
      DADDR        => "0010110",  -- The address for reading AUX channel 6
      DCLK         => clk100,
      DEN          => '1',
      DI           => (others => '0'),
      DWE          => '0'
   );
end Behavioral;

And here is the XDC file for the Basys3:

set_property PACKAGE_PIN W5 [get_ports clk100]                            
    set_property IOSTANDARD LVCMOS33 [get_ports clk100]
    create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk100]
## LEDs
set_property PACKAGE_PIN U16 [get_ports {led[0]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property PACKAGE_PIN E19 [get_ports {led[1]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property PACKAGE_PIN U19 [get_ports {led[2]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property PACKAGE_PIN V19 [get_ports {led[3]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property PACKAGE_PIN W18 [get_ports {led[4]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
set_property PACKAGE_PIN U15 [get_ports {led[5]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
set_property PACKAGE_PIN U14 [get_ports {led[6]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
set_property PACKAGE_PIN V14 [get_ports {led[7]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
set_property PACKAGE_PIN V13 [get_ports {led[8]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
set_property PACKAGE_PIN V3 [get_ports {led[9]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
set_property PACKAGE_PIN W3 [get_ports {led[10]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
set_property PACKAGE_PIN U3 [get_ports {led[11]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
set_property PACKAGE_PIN P3 [get_ports {led[12]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
set_property PACKAGE_PIN N3 [get_ports {led[13]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
set_property PACKAGE_PIN P1 [get_ports {led[14]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
set_property PACKAGE_PIN L1 [get_ports {led[15]}]                    
    set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
##Pmod Header JXADC
##Sch name = XA1_P
set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]                
    set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
##Sch name = XA2_P
set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]                
    set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
##Sch name = XA3_P
set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]                
    set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
##Sch name = XA4_P
set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]                
    set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
##Sch name = XA1_N
set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]                
    set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
##Sch name = XA2_N
set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]                
    set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
##Sch name = XA3_N
set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]                
    set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
##Sch name = XA4_N
set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]                
    set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]

When downloaded to your board, the value displayed in binary on the the LEDs should reflect the voltage on Pin 0 if the PXADC. I tested just by pushing some header pins into the PMOD and touching the pin - not exactly a complete test, but enough to show that it does something.

NOTE: THE FULL SCALE VOLTAGE FOR THE XADC IS 1V, so some crafty planning might be required to interface to it.

Hi Hamster,

1. Is it INIT_49 => X"coco", -- for channels 6,7,14,15?

INIT_49 => X"000CC", -- CHSEL2 - enable aux analog channels 6,7,14,15

2. I use Basys3 (xc7a35tcpg236-1) board. Is it compulsory to specify the below?

SIM_DEVICE       => "7SERIES",    -- Select target device (values)

3. Should I initialize DADDR like this one?

DADDR        => "0010110",  -- The address for reading AUX channel 6

Thank you,

Shruthi.

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Hi Shruthi,

1) check http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf page 60 - table 4-4. The channel numbering is a little bit odd.

2) Not sure,  as XADC is only available on 7-Series FPGAs. I guess it is for future chips, and I guess it only matters for simulation.

3) If you want to only read channel 6, yes. See figure 3-1 on page 36. 

Mike

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